2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2001 Tsubai Masanari.
5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
7 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC.
38 * This controller can only perform complete transfers, it does not provide
39 * low-level control over sending start/repeat-start/stop sequences on the bus.
40 * In addition, bugs in the silicon make it somewhat difficult to perform a
41 * repeat-start, and limit the repeat-start to a read following a write on
42 * the same slave device. (The i2c protocol allows a repeat start to change
43 * direction or not, and change slave address or not at any time.)
45 * The repeat-start bug and workaround are described in a problem report at
46 * https://github.com/raspberrypi/linux/issues/254 with the crucial part being
47 * in a comment block from a fragment of a GPU i2c driver, containing this:
49 * -----------------------------------------------------------------------------
50 * - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count
51 * - in the IDLE state if start is set.
53 * - We want to generate a ReSTART not a STOP at the end of the TX phase. In
54 * - order to do that we must ensure the state machine goes RACK1 -> RACK2 ->
55 * - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1).
57 * - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have
58 * - already set, ready to be sampled:
59 * - READ ; rw_bit <= I2CC bit 0 -- must be "read"
60 * - ST; start <= I2CC bit 7 -- must be "Go" in order to not issue STOP
61 * - DLEN; xfer_count <= I2CDLEN -- must be equal to our read amount
63 * - The plan to do this is:
64 * - 1. Start the sub-address write, but don't let it finish
65 * - (keep xfer_count > 0)
66 * - 2. Populate READ, DLEN and ST in preparation for ReSTART read sequence
67 * - 3. Let TX finish (write the rest of the data)
68 * - 4. Read back data as it arrives
69 * -----------------------------------------------------------------------------
71 * The transfer function below scans the list of messages passed to it, looking
72 * for a read following a write to the same slave. When it finds that, it
73 * starts the write without prefilling the tx fifo, which holds xfer_count>0,
74 * then presets the direction, length, and start command for the following read,
75 * as described above. Then the tx fifo is filled and the rest of the transfer
76 * proceeds as normal, with the controller automatically supplying a
77 * repeat-start on the bus when the write operation finishes.
79 * XXX I suspect the controller may be able to do a repeat-start on any
80 * write->read or write->write transition, even when the slave addresses differ.
81 * It's unclear whether the slave address can be prestaged along with the
82 * direction and length while the write xfer_count is being held at zero. In
83 * fact, if it can't do this, then it couldn't be used to read EDID data.
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/mutex.h>
93 #include <machine/resource.h>
94 #include <machine/bus.h>
96 #include <sys/sysctl.h>
98 #include <dev/iicbus/iicbus.h>
99 #include <dev/iicbus/iiconf.h>
100 #include <dev/ofw/ofw_bus.h>
101 #include <dev/ofw/ofw_bus_subr.h>
103 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h>
104 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h>
106 #include "iicbus_if.h"
108 static struct ofw_compat_data compat_data[] = {
109 {"broadcom,bcm2835-bsc", 1},
110 {"brcm,bcm2708-i2c", 1},
111 {"brcm,bcm2835-i2c", 1},
115 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \
116 if ((lvl) <= (sc)->sc_debug) \
117 device_printf((sc)->sc_dev, fmt, ##args)
119 #define DEBUGF(sc, lvl, fmt, args...) \
120 if ((lvl) <= (sc)->sc_debug) \
123 static void bcm_bsc_intr(void *);
124 static int bcm_bsc_detach(device_t);
127 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
132 mtx_assert(&sc->sc_mtx, MA_OWNED);
133 reg = BCM_BSC_READ(sc, off);
136 BCM_BSC_WRITE(sc, off, reg);
140 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
142 struct bcm_bsc_softc *sc;
145 sc = (struct bcm_bsc_softc *)arg1;
147 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
152 clk = BCM_BSC_CORE_CLK / clk;
154 return (sysctl_handle_int(oidp, &clk, 0, req));
158 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS)
160 struct bcm_bsc_softc *sc;
164 sc = (struct bcm_bsc_softc *)arg1;
167 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT);
170 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req);
171 if (error != 0 || req->newptr == NULL)
175 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff);
182 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS)
184 struct bcm_bsc_softc *sc;
188 sc = (struct bcm_bsc_softc *)arg1;
191 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
194 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
195 if (error != 0 || req->newptr == NULL)
199 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
200 clk = BCM_BSC_CORE_CLK / clk;
203 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);
210 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS)
212 struct bcm_bsc_softc *sc;
216 sc = (struct bcm_bsc_softc *)arg1;
219 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
222 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
223 if (error != 0 || req->newptr == NULL)
227 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
228 clk = BCM_BSC_CORE_CLK / clk;
231 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);
238 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
240 struct sysctl_ctx_list *ctx;
241 struct sysctl_oid *tree_node;
242 struct sysctl_oid_list *tree;
245 * Add system sysctl tree/handlers.
247 ctx = device_get_sysctl_ctx(sc->sc_dev);
248 tree_node = device_get_sysctl_tree(sc->sc_dev);
249 tree = SYSCTL_CHILDREN(tree_node);
250 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency",
251 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
252 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
253 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
254 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
255 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout");
256 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay",
257 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
258 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay");
259 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay",
260 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
261 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay");
262 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug",
263 CTLFLAG_RWTUN, &sc->sc_debug, 0,
264 "Enable debug; 1=reads/writes, 2=add starts/stops");
268 bcm_bsc_reset(struct bcm_bsc_softc *sc)
271 /* Enable the BSC Controller, disable interrupts. */
272 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
273 /* Clear pending interrupts. */
274 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT |
275 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE);
276 /* Clear the FIFO. */
277 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0,
278 BCM_BSC_CTRL_CLEAR0);
282 bcm_bsc_probe(device_t dev)
285 if (!ofw_bus_status_okay(dev))
288 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
291 device_set_desc(dev, "BCM2708/2835 BSC controller");
293 return (BUS_PROBE_DEFAULT);
297 bcm_bsc_attach(device_t dev)
299 struct bcm_bsc_softc *sc;
302 sc = device_get_softc(dev);
306 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
308 if (!sc->sc_mem_res) {
309 device_printf(dev, "cannot allocate memory window\n");
313 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
314 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
317 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
318 RF_ACTIVE | RF_SHAREABLE);
319 if (!sc->sc_irq_res) {
320 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
321 device_printf(dev, "cannot allocate interrupt\n");
325 /* Hook up our interrupt handler. */
326 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
327 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) {
328 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
329 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
330 device_printf(dev, "cannot setup the interrupt handler\n");
334 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF);
336 bcm_bsc_sysctl_init(sc);
338 /* Enable the BSC controller. Flush the FIFO. */
343 sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
344 if (sc->sc_iicbus == NULL) {
349 /* Probe and attach the iicbus when interrupts are available. */
350 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
356 bcm_bsc_detach(device_t dev)
358 struct bcm_bsc_softc *sc;
360 bus_generic_detach(dev);
362 sc = device_get_softc(dev);
363 if (sc->sc_iicbus != NULL)
364 device_delete_child(dev, sc->sc_iicbus);
365 mtx_destroy(&sc->sc_mtx);
367 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
369 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
371 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
377 bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc)
381 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */
383 if (sc->sc_resid == 0) {
384 sc->sc_data = sc->sc_curmsg->buf;
385 sc->sc_dlen = sc->sc_curmsg->len;
386 sc->sc_resid = sc->sc_dlen;
390 *sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA);
391 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data);
395 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
396 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD));
397 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD));
401 bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc)
405 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */
407 if (sc->sc_resid == 0) {
408 sc->sc_data = sc->sc_curmsg->buf;
409 sc->sc_dlen = sc->sc_curmsg->len;
410 sc->sc_resid = sc->sc_dlen;
414 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data);
415 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data);
419 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
420 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD));
422 * If a repeat-start was pending and we just hit the end of a tx
423 * buffer, see if it's also the end of the writes that preceeded
424 * the repeat-start. If so, log the repeat-start and the start
425 * of the following read, and return because we're not writing
426 * anymore (and TXD will be true because there's room to write
429 if (sc->sc_replen > 0 && sc->sc_resid == 0) {
430 sc->sc_replen -= sc->sc_dlen;
431 if (sc->sc_replen == 0) {
432 DEBUGF(sc, 1, " err=0\n");
433 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n",
434 sc->sc_curmsg->slave | 0x01);
436 "read 0x%02x len %d: ",
437 sc->sc_curmsg->slave | 0x01,
439 sc->sc_flags |= BCM_I2C_READ;
443 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD));
447 bcm_bsc_intr(void *arg)
449 struct bcm_bsc_softc *sc;
452 sc = (struct bcm_bsc_softc *)arg;
456 /* The I2C interrupt is shared among all the BSC controllers. */
457 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) {
462 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
463 DEBUGF(sc, 4, " <intrstatus=0x%08x> ", status);
465 /* RXD and DONE can assert together, empty fifo before checking done. */
466 if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD))
467 bcm_bsc_empty_rx_fifo(sc);
469 /* Check for completion. */
470 if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) {
471 sc->sc_flags |= BCM_I2C_DONE;
472 if (status & BCM_BSC_STATUS_ERRBITS)
473 sc->sc_flags |= BCM_I2C_ERROR;
474 /* Disable interrupts. */
477 } else if (!(sc->sc_flags & BCM_I2C_READ)) {
479 * Don't check for TXD until after determining whether the
480 * transfer is complete; TXD will be asserted along with ERR or
481 * DONE if there is room in the fifo.
483 if ((status & BCM_BSC_STATUS_TXD) && sc->sc_totlen > 0)
484 bcm_bsc_fill_tx_fifo(sc);
491 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
493 struct bcm_bsc_softc *sc;
494 struct iic_msg *endmsgs, *nxtmsg;
495 uint32_t readctl, status;
498 uint8_t curisread, curslave, nxtisread, nxtslave;
500 sc = device_get_softc(dev);
503 /* If the controller is busy wait until it is available. */
504 while (sc->sc_flags & BCM_I2C_BUSY)
505 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0);
507 /* Now we have control over the BSC controller. */
508 sc->sc_flags = BCM_I2C_BUSY;
510 DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs);
512 /* Clear the FIFO and the pending interrupts. */
516 * Perform all the transfers requested in the array of msgs. Note that
517 * it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance
518 * sc->sc_curmsg through the array of messages, as the data from each
519 * message is fully consumed, but it is this loop that notices when we
520 * have no more messages to process.
524 sc->sc_curmsg = msgs;
525 endmsgs = &msgs[nmsgs];
526 while (sc->sc_curmsg < endmsgs) {
528 curslave = sc->sc_curmsg->slave >> 1;
529 curisread = sc->sc_curmsg->flags & IIC_M_RD;
531 sc->sc_totlen = sc->sc_curmsg->len;
533 * Scan for scatter/gather IO (same slave and direction) or
534 * repeat-start (read following write for the same slave).
536 for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) {
537 nxtslave = nxtmsg->slave >> 1;
538 if (curslave == nxtslave) {
539 nxtisread = nxtmsg->flags & IIC_M_RD;
540 if (curisread == nxtisread) {
542 * Same slave and direction, this
543 * message will be part of the same
544 * transfer as the previous one.
546 sc->sc_totlen += nxtmsg->len;
548 } else if (curisread == IIC_M_WR) {
550 * Read after write to same slave means
551 * repeat-start, remember how many bytes
552 * come before the repeat-start, switch
553 * the direction to IIC_M_RD, and gather
554 * up following reads to the same slave.
556 curisread = IIC_M_RD;
557 sc->sc_replen = sc->sc_totlen;
558 sc->sc_totlen += nxtmsg->len;
566 * curslave and curisread temporaries from above may refer to
567 * the after-repstart msg, reset them to reflect sc_curmsg.
569 curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0;
570 curslave = sc->sc_curmsg->slave | curisread;
572 /* Write the slave address. */
573 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1);
575 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", curslave);
578 * Either set up read length and direction variables for a
579 * simple transfer or get the hardware started on the first
580 * piece of a transfer that involves a repeat-start and set up
581 * the read length and direction vars for the second piece.
583 if (sc->sc_replen == 0) {
584 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ",
585 (curisread) ? "read" : "write", curslave,
587 curlen = sc->sc_totlen;
589 readctl = BCM_BSC_CTRL_READ;
590 sc->sc_flags |= BCM_I2C_READ;
593 sc->sc_flags &= ~BCM_I2C_READ;
596 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ",
597 (curisread) ? "read" : "write", curslave,
601 * Start the write transfer with an empty fifo and wait
602 * for the 'transfer active' status bit to light up;
603 * that indicates that the hardware has latched the
604 * direction and length for the write, and we can safely
605 * reload those registers and issue the start for the
606 * following read; interrupts are not enabled here.
608 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen);
609 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN |
612 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
613 if (status & BCM_BSC_STATUS_ERR) {
614 /* no ACK on slave addr */
618 } while ((status & BCM_BSC_STATUS_TA) == 0);
620 * Set curlen and readctl for the repeat-start read that
621 * we need to set up below, but set sc_flags to write,
622 * because that is the operation in progress right now.
624 curlen = sc->sc_totlen - sc->sc_replen;
625 readctl = BCM_BSC_CTRL_READ;
626 sc->sc_flags &= ~BCM_I2C_READ;
630 * Start the transfer with interrupts enabled, then if doing a
631 * write, fill the tx fifo. Not prefilling the fifo until after
632 * this start command is the key workaround for making
633 * repeat-start work, and it's harmless to do it in this order
634 * for a regular write too.
636 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen);
637 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN |
638 BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL);
640 if (!(sc->sc_curmsg->flags & IIC_M_RD)) {
641 bcm_bsc_fill_tx_fifo(sc);
644 /* Wait for the transaction to complete. */
645 while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) {
646 err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz);
648 /* Check for errors. */
649 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR))
652 DEBUGF(sc, 1, " err=%d\n", err);
653 DEVICE_DEBUGF(sc, 2, "stop\n");
658 /* Disable interrupts, clean fifo, etc. */
661 /* Clean the controller flags. */
664 /* Wake up the threads waiting for bus. */
673 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
675 struct bcm_bsc_softc *sc;
678 sc = device_get_softc(dev);
681 if (sc->sc_iicbus == NULL)
684 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
685 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq);
688 return (IIC_ENOADDR);
692 bcm_bsc_get_node(device_t bus, device_t dev)
695 /* We only have one child, the I2C bus, which needs our own node. */
696 return (ofw_bus_get_node(bus));
699 static device_method_t bcm_bsc_methods[] = {
700 /* Device interface */
701 DEVMETHOD(device_probe, bcm_bsc_probe),
702 DEVMETHOD(device_attach, bcm_bsc_attach),
703 DEVMETHOD(device_detach, bcm_bsc_detach),
705 /* iicbus interface */
706 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset),
707 DEVMETHOD(iicbus_callback, iicbus_null_callback),
708 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer),
710 /* ofw_bus interface */
711 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node),
716 static devclass_t bcm_bsc_devclass;
718 static driver_t bcm_bsc_driver = {
721 sizeof(struct bcm_bsc_softc),
724 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0);
725 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0);