2 * Copyright (c) 2001 Tsubai Masanari.
3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <machine/resource.h>
40 #include <machine/bus.h>
42 #include <sys/sysctl.h>
44 #include <dev/iicbus/iicbus.h>
45 #include <dev/iicbus/iiconf.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
50 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h>
51 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h>
53 #include "iicbus_if.h"
55 static void bcm_bsc_intr(void *);
56 static int bcm_bsc_detach(device_t);
59 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
64 mtx_assert(&sc->sc_mtx, MA_OWNED);
65 reg = BCM_BSC_READ(sc, off);
68 BCM_BSC_WRITE(sc, off, reg);
72 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
74 struct bcm_bsc_softc *sc;
77 sc = (struct bcm_bsc_softc *)arg1;
79 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
84 clk = BCM_BSC_CORE_CLK / clk;
86 return (sysctl_handle_int(oidp, &clk, 0, req));
90 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS)
92 struct bcm_bsc_softc *sc;
96 sc = (struct bcm_bsc_softc *)arg1;
99 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT);
102 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req);
103 if (error != 0 || req->newptr == NULL)
107 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff);
114 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS)
116 struct bcm_bsc_softc *sc;
120 sc = (struct bcm_bsc_softc *)arg1;
123 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
126 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
127 if (error != 0 || req->newptr == NULL)
131 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
132 clk = BCM_BSC_CORE_CLK / clk;
135 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);
142 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS)
144 struct bcm_bsc_softc *sc;
148 sc = (struct bcm_bsc_softc *)arg1;
151 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
154 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
155 if (error != 0 || req->newptr == NULL)
159 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
160 clk = BCM_BSC_CORE_CLK / clk;
163 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);
170 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
172 struct sysctl_ctx_list *ctx;
173 struct sysctl_oid *tree_node;
174 struct sysctl_oid_list *tree;
177 * Add system sysctl tree/handlers.
179 ctx = device_get_sysctl_ctx(sc->sc_dev);
180 tree_node = device_get_sysctl_tree(sc->sc_dev);
181 tree = SYSCTL_CHILDREN(tree_node);
182 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency",
183 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
184 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
185 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
186 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
187 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout");
188 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay",
189 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
190 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay");
191 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay",
192 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
193 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay");
197 bcm_bsc_reset(struct bcm_bsc_softc *sc)
200 /* Enable the BSC Controller, disable interrupts. */
201 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
202 /* Clear pending interrupts. */
203 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT |
204 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE);
205 /* Clear the FIFO. */
206 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0,
207 BCM_BSC_CTRL_CLEAR0);
211 bcm_bsc_probe(device_t dev)
214 if (!ofw_bus_status_okay(dev))
217 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-bsc"))
220 device_set_desc(dev, "BCM2708/2835 BSC controller");
222 return (BUS_PROBE_DEFAULT);
226 bcm_bsc_attach(device_t dev)
228 struct bcm_bsc_softc *sc;
233 sc = device_get_softc(dev);
237 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
239 if (!sc->sc_mem_res) {
240 device_printf(dev, "cannot allocate memory window\n");
244 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
245 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
247 /* Check the unit we are attaching by its base address. */
248 start = rman_get_start(sc->sc_mem_res);
249 for (i = 0; i < nitems(bcm_bsc_pins); i++) {
250 if (bcm_bsc_pins[i].start == start)
253 if (i == nitems(bcm_bsc_pins)) {
254 device_printf(dev, "only bsc0 and bsc1 are supported\n");
259 * Configure the GPIO pins to ALT0 function to enable BSC control
262 gpio = devclass_get_device(devclass_find("gpio"), 0);
264 device_printf(dev, "cannot find gpio0\n");
267 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0);
268 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0);
271 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
272 RF_ACTIVE | RF_SHAREABLE);
273 if (!sc->sc_irq_res) {
274 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
275 device_printf(dev, "cannot allocate interrupt\n");
279 /* Hook up our interrupt handler. */
280 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
281 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) {
282 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
283 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
284 device_printf(dev, "cannot setup the interrupt handler\n");
288 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF);
290 bcm_bsc_sysctl_init(sc);
292 /* Enable the BSC controller. Flush the FIFO. */
297 sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
298 if (sc->sc_iicbus == NULL) {
303 return (bus_generic_attach(dev));
307 bcm_bsc_detach(device_t dev)
309 struct bcm_bsc_softc *sc;
311 bus_generic_detach(dev);
313 sc = device_get_softc(dev);
314 mtx_destroy(&sc->sc_mtx);
316 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
318 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
320 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
326 bcm_bsc_intr(void *arg)
328 struct bcm_bsc_softc *sc;
331 sc = (struct bcm_bsc_softc *)arg;
335 /* The I2C interrupt is shared among all the BSC controllers. */
336 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) {
341 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
343 /* Check for errors. */
344 if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) {
345 /* Disable interrupts. */
347 sc->sc_flags |= BCM_I2C_ERROR;
353 if (sc->sc_flags & BCM_I2C_READ) {
354 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) {
355 *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA);
357 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
360 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) {
361 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++);
363 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
367 if (status & BCM_BSC_STATUS_DONE) {
368 /* Disable interrupts. */
377 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
379 struct bcm_bsc_softc *sc;
380 uint32_t intr, read, status;
383 sc = device_get_softc(dev);
386 /* If the controller is busy wait until it is available. */
387 while (sc->sc_flags & BCM_I2C_BUSY)
388 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0);
390 /* Now we have control over the BSC controller. */
391 sc->sc_flags = BCM_I2C_BUSY;
393 /* Clear the FIFO and the pending interrupts. */
397 for (i = 0; i < nmsgs; i++) {
399 /* Write the slave address. */
400 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1);
402 /* Write the data length. */
403 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len);
405 sc->sc_data = msgs[i].buf;
406 sc->sc_resid = msgs[i].len;
407 if ((msgs[i].flags & IIC_M_RD) == 0) {
408 /* Fill up the TX FIFO. */
409 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
410 while (sc->sc_resid > 0 &&
411 (status & BCM_BSC_STATUS_TXD)) {
412 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data);
415 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
418 intr = BCM_BSC_CTRL_INTT;
419 sc->sc_flags &= ~BCM_I2C_READ;
421 sc->sc_flags |= BCM_I2C_READ;
422 read = BCM_BSC_CTRL_READ;
423 intr = BCM_BSC_CTRL_INTR;
425 intr |= BCM_BSC_CTRL_INTD;
427 /* Start the transfer. */
428 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN |
429 BCM_BSC_CTRL_ST | read | intr);
431 /* Wait for the transaction to complete. */
432 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bsciow", hz);
434 /* Check for errors. */
435 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR))
441 /* Clean the controller flags. */
444 /* Wake up the threads waiting for bus. */
453 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
455 struct bcm_bsc_softc *sc;
458 sc = device_get_softc(dev);
461 if (sc->sc_iicbus == NULL)
464 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
465 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq);
468 return (IIC_ENOADDR);
472 bcm_bsc_get_node(device_t bus, device_t dev)
475 /* We only have one child, the I2C bus, which needs our own node. */
476 return (ofw_bus_get_node(bus));
479 static device_method_t bcm_bsc_methods[] = {
480 /* Device interface */
481 DEVMETHOD(device_probe, bcm_bsc_probe),
482 DEVMETHOD(device_attach, bcm_bsc_attach),
483 DEVMETHOD(device_detach, bcm_bsc_detach),
485 /* iicbus interface */
486 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset),
487 DEVMETHOD(iicbus_callback, iicbus_null_callback),
488 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer),
490 /* ofw_bus interface */
491 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node),
496 static devclass_t bcm_bsc_devclass;
498 static driver_t bcm_bsc_driver = {
501 sizeof(struct bcm_bsc_softc),
504 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0);
505 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0);