2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_platform.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <sys/sysctl.h>
46 #include <machine/bus.h>
47 #include <machine/intr.h>
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
52 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
61 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
62 printf(fmt,##args); } while (0)
64 #define dprintf(fmt, args...)
67 #define BCM_GPIO_IRQS 4
68 #define BCM_GPIO_PINS 54
69 #define BCM_GPIO_PINS_PER_BANK 32
70 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
71 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
73 static struct resource_spec bcm_gpio_res_spec[] = {
74 { SYS_RES_MEMORY, 0, RF_ACTIVE },
75 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */
76 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */
77 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* bank 1 interrupt (mirrored) */
78 { SYS_RES_IRQ, 3, RF_ACTIVE }, /* bank 0-1 interrupt (united) */
82 struct bcm_gpio_sysctl {
83 struct bcm_gpio_softc *sc;
88 struct bcm_gpio_irqsrc {
89 struct intr_irqsrc bgi_isrc;
96 struct bcm_gpio_softc {
100 struct resource * sc_res[BCM_GPIO_IRQS + 1];
101 bus_space_tag_t sc_bst;
102 bus_space_handle_t sc_bsh;
103 void * sc_intrhand[BCM_GPIO_IRQS];
106 int sc_ro_pins[BCM_GPIO_PINS];
107 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS];
109 struct intr_event * sc_events[BCM_GPIO_PINS];
111 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS];
113 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS];
115 enum intr_trigger sc_irq_trigger[BCM_GPIO_PINS];
116 enum intr_polarity sc_irq_polarity[BCM_GPIO_PINS];
126 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
127 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
128 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
129 #define BCM_GPIO_WRITE(_sc, _off, _val) \
130 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
131 #define BCM_GPIO_READ(_sc, _off) \
132 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
133 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \
134 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits))
135 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \
136 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits)
137 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK)
138 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK))
140 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */
141 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */
142 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */
143 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */
144 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */
145 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */
146 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */
147 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */
148 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */
149 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */
150 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */
151 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */
152 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */
154 static struct bcm_gpio_softc *bcm_gpio_sc = NULL;
157 static int bcm_gpio_intr_bank0(void *arg);
158 static int bcm_gpio_intr_bank1(void *arg);
159 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc);
160 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc);
164 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin)
168 for (i = 0; i < sc->sc_ro_npins; i++)
169 if (pin == sc->sc_ro_pins[i])
175 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin)
177 uint32_t bank, func, offset;
179 /* Five banks, 10 pins per bank, 3 bits per pin. */
181 offset = (pin - bank * 10) * 3;
184 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7;
191 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize)
196 strncpy(buf, "input", bufsize);
198 case BCM_GPIO_OUTPUT:
199 strncpy(buf, "output", bufsize);
202 strncpy(buf, "alt0", bufsize);
205 strncpy(buf, "alt1", bufsize);
208 strncpy(buf, "alt2", bufsize);
211 strncpy(buf, "alt3", bufsize);
214 strncpy(buf, "alt4", bufsize);
217 strncpy(buf, "alt5", bufsize);
220 strncpy(buf, "invalid", bufsize);
225 bcm_gpio_str_func(char *func, uint32_t *nfunc)
228 if (strcasecmp(func, "input") == 0)
229 *nfunc = BCM_GPIO_INPUT;
230 else if (strcasecmp(func, "output") == 0)
231 *nfunc = BCM_GPIO_OUTPUT;
232 else if (strcasecmp(func, "alt0") == 0)
233 *nfunc = BCM_GPIO_ALT0;
234 else if (strcasecmp(func, "alt1") == 0)
235 *nfunc = BCM_GPIO_ALT1;
236 else if (strcasecmp(func, "alt2") == 0)
237 *nfunc = BCM_GPIO_ALT2;
238 else if (strcasecmp(func, "alt3") == 0)
239 *nfunc = BCM_GPIO_ALT3;
240 else if (strcasecmp(func, "alt4") == 0)
241 *nfunc = BCM_GPIO_ALT4;
242 else if (strcasecmp(func, "alt5") == 0)
243 *nfunc = BCM_GPIO_ALT5;
251 bcm_gpio_func_flag(uint32_t nfunc)
256 return (GPIO_PIN_INPUT);
257 case BCM_GPIO_OUTPUT:
258 return (GPIO_PIN_OUTPUT);
264 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f)
266 uint32_t bank, data, offset;
268 /* Must be called with lock held. */
269 BCM_GPIO_LOCK_ASSERT(sc);
271 /* Five banks, 10 pins per bank, 3 bits per pin. */
273 offset = (pin - bank * 10) * 3;
275 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank));
276 data &= ~(7 << offset);
277 data |= (f << offset);
278 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data);
282 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state)
286 /* Must be called with lock held. */
287 BCM_GPIO_LOCK_ASSERT(sc);
289 bank = BCM_GPIO_BANK(pin);
290 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state);
291 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin));
292 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0);
293 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0);
297 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc)
299 struct bcm_gpio_softc *sc;
302 sc = device_get_softc(dev);
305 /* Disable pull-up or pull-down on pin. */
306 bcm_gpio_set_pud(sc, pin, BCM_GPIO_NONE);
308 /* And now set the pin function. */
309 bcm_gpio_set_function(sc, pin, nfunc);
311 /* Update the pin flags. */
312 for (i = 0; i < sc->sc_gpio_npins; i++) {
313 if (sc->sc_gpio_pins[i].gp_pin == pin)
316 if (i < sc->sc_gpio_npins)
317 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc);
323 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin,
330 * Manage input/output.
332 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
333 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
334 if (flags & GPIO_PIN_OUTPUT) {
335 pin->gp_flags |= GPIO_PIN_OUTPUT;
336 bcm_gpio_set_function(sc, pin->gp_pin,
339 pin->gp_flags |= GPIO_PIN_INPUT;
340 bcm_gpio_set_function(sc, pin->gp_pin,
345 /* Manage Pull-up/pull-down. */
346 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
347 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
348 if (flags & GPIO_PIN_PULLUP) {
349 pin->gp_flags |= GPIO_PIN_PULLUP;
350 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP);
352 pin->gp_flags |= GPIO_PIN_PULLDOWN;
353 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN);
356 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE);
362 bcm_gpio_get_bus(device_t dev)
364 struct bcm_gpio_softc *sc;
366 sc = device_get_softc(dev);
368 return (sc->sc_busdev);
372 bcm_gpio_pin_max(device_t dev, int *maxpin)
375 *maxpin = BCM_GPIO_PINS - 1;
380 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
382 struct bcm_gpio_softc *sc = device_get_softc(dev);
385 for (i = 0; i < sc->sc_gpio_npins; i++) {
386 if (sc->sc_gpio_pins[i].gp_pin == pin)
390 if (i >= sc->sc_gpio_npins)
394 *caps = sc->sc_gpio_pins[i].gp_caps;
401 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
403 struct bcm_gpio_softc *sc = device_get_softc(dev);
406 for (i = 0; i < sc->sc_gpio_npins; i++) {
407 if (sc->sc_gpio_pins[i].gp_pin == pin)
411 if (i >= sc->sc_gpio_npins)
415 *flags = sc->sc_gpio_pins[i].gp_flags;
422 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
424 struct bcm_gpio_softc *sc = device_get_softc(dev);
427 for (i = 0; i < sc->sc_gpio_npins; i++) {
428 if (sc->sc_gpio_pins[i].gp_pin == pin)
432 if (i >= sc->sc_gpio_npins)
436 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
443 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
445 struct bcm_gpio_softc *sc = device_get_softc(dev);
448 for (i = 0; i < sc->sc_gpio_npins; i++) {
449 if (sc->sc_gpio_pins[i].gp_pin == pin)
453 if (i >= sc->sc_gpio_npins)
456 /* We never touch on read-only/reserved pins. */
457 if (bcm_gpio_pin_is_ro(sc, pin))
460 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
466 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
468 struct bcm_gpio_softc *sc = device_get_softc(dev);
472 for (i = 0; i < sc->sc_gpio_npins; i++) {
473 if (sc->sc_gpio_pins[i].gp_pin == pin)
476 if (i >= sc->sc_gpio_npins)
478 /* We never write to read-only/reserved pins. */
479 if (bcm_gpio_pin_is_ro(sc, pin))
482 bank = BCM_GPIO_BANK(pin);
484 reg = BCM_GPIO_GPSET(bank);
486 reg = BCM_GPIO_GPCLR(bank);
487 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
494 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
496 struct bcm_gpio_softc *sc = device_get_softc(dev);
497 uint32_t bank, reg_data;
500 for (i = 0; i < sc->sc_gpio_npins; i++) {
501 if (sc->sc_gpio_pins[i].gp_pin == pin)
504 if (i >= sc->sc_gpio_npins)
506 bank = BCM_GPIO_BANK(pin);
508 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
510 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0;
516 bcm_gpio_pin_toggle(device_t dev, uint32_t pin)
518 struct bcm_gpio_softc *sc = device_get_softc(dev);
519 uint32_t bank, data, reg;
522 for (i = 0; i < sc->sc_gpio_npins; i++) {
523 if (sc->sc_gpio_pins[i].gp_pin == pin)
526 if (i >= sc->sc_gpio_npins)
528 /* We never write to read-only/reserved pins. */
529 if (bcm_gpio_pin_is_ro(sc, pin))
532 bank = BCM_GPIO_BANK(pin);
533 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
534 if (data & BCM_GPIO_MASK(pin))
535 reg = BCM_GPIO_GPCLR(bank);
537 reg = BCM_GPIO_GPSET(bank);
538 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
545 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS)
548 struct bcm_gpio_softc *sc;
549 struct bcm_gpio_sysctl *sc_sysctl;
556 /* Get the current pin function. */
557 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin);
558 bcm_gpio_func_str(nfunc, buf, sizeof(buf));
560 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
561 if (error != 0 || req->newptr == NULL)
563 /* Ignore changes on read-only pins. */
564 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin))
566 /* Parse the user supplied string and check for a valid pin function. */
567 if (bcm_gpio_str_func(buf, &nfunc) != 0)
570 /* Update the pin alternate function. */
571 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc);
577 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc)
580 struct bcm_gpio_sysctl *sc_sysctl;
581 struct sysctl_ctx_list *ctx;
582 struct sysctl_oid *tree_node, *pin_node, *pinN_node;
583 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree;
587 * Add per-pin sysctl tree/handlers.
589 ctx = device_get_sysctl_ctx(sc->sc_dev);
590 tree_node = device_get_sysctl_tree(sc->sc_dev);
591 tree = SYSCTL_CHILDREN(tree_node);
592 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin",
593 CTLFLAG_RD, NULL, "GPIO Pins");
594 pin_tree = SYSCTL_CHILDREN(pin_node);
596 for (i = 0; i < sc->sc_gpio_npins; i++) {
598 snprintf(pinbuf, sizeof(pinbuf), "%d", i);
599 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf,
600 CTLFLAG_RD, NULL, "GPIO Pin");
601 pinN_tree = SYSCTL_CHILDREN(pinN_node);
603 sc->sc_sysctl[i].sc = sc;
604 sc_sysctl = &sc->sc_sysctl[i];
606 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin;
607 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function",
608 CTLFLAG_RW | CTLTYPE_STRING, sc_sysctl,
609 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc,
610 "A", "Pin Function");
615 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node,
616 const char *propname, const char *label)
618 int i, need_comma, npins, range_start, range_stop;
621 /* Get the property data. */
622 npins = OF_getencprop_alloc(node, propname, sizeof(*pins),
627 free(pins, M_OFWPROP);
630 for (i = 0; i < npins; i++)
631 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i];
632 sc->sc_ro_npins += npins;
634 device_printf(sc->sc_dev, "%s pins: ", label);
635 range_start = range_stop = pins[0];
636 for (i = 1; i < npins; i++) {
637 if (pins[i] != range_stop + 1) {
640 if (range_start != range_stop)
641 printf("%d-%d", range_start, range_stop);
643 printf("%d", range_start);
644 range_start = range_stop = pins[i];
651 if (range_start != range_stop)
652 printf("%d-%d.\n", range_start, range_stop);
654 printf("%d.\n", range_start);
655 free(pins, M_OFWPROP);
661 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc)
664 phandle_t gpio, node, reserved;
667 /* Get read-only pins. */
668 gpio = ofw_bus_get_node(sc->sc_dev);
669 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only",
672 /* Traverse the GPIO subnodes to find the reserved pins node. */
674 node = OF_child(gpio);
675 while ((node != 0) && (reserved == 0)) {
676 len = OF_getprop_alloc(node, "name", 1, (void **)&name);
679 if (strcmp(name, "reserved") == 0)
681 free(name, M_OFWPROP);
682 node = OF_peer(node);
686 /* Get the reserved pins. */
687 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins",
696 bcm_gpio_intr(void *arg)
699 struct bcm_gpio_softc *sc;
700 struct intr_event *event;
701 uint32_t bank, mask, reg;
703 sc = (struct bcm_gpio_softc *)arg;
706 for (irq = 0; irq < BCM_GPIO_PINS; irq++) {
707 bank = BCM_GPIO_BANK(irq);
708 mask = BCM_GPIO_MASK(irq);
709 if (bank != bank_last) {
710 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));
714 event = sc->sc_events[irq];
715 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
716 intr_event_handle(event, NULL);
718 device_printf(sc->sc_dev, "Stray IRQ %d\n",
721 /* Clear the Status bit by writing '1' to it. */
722 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), mask);
726 return (FILTER_HANDLED);
731 bcm_gpio_probe(device_t dev)
734 if (!ofw_bus_status_okay(dev))
737 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-gpio"))
740 device_set_desc(dev, "BCM2708/2835 GPIO controller");
741 return (BUS_PROBE_DEFAULT);
746 bcm_gpio_intr_attach(device_t dev)
748 struct bcm_gpio_softc *sc;
751 * Only first two interrupt lines are used. Third line is
752 * mirrored second line and forth line is common for all banks.
754 sc = device_get_softc(dev);
755 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL)
758 if (bcm_gpio_pic_attach(sc) != 0) {
759 device_printf(dev, "unable to attach PIC\n");
762 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE,
763 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0)
765 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE,
766 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0)
773 bcm_gpio_intr_detach(device_t dev)
775 struct bcm_gpio_softc *sc;
777 sc = device_get_softc(dev);
778 if (sc->sc_intrhand[0] != NULL)
779 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]);
780 if (sc->sc_intrhand[1] != NULL)
781 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]);
783 bcm_gpio_pic_detach(sc);
788 bcm_gpio_intr_attach(device_t dev)
790 struct bcm_gpio_softc *sc;
793 sc = device_get_softc(dev);
794 for (i = 0; i < BCM_GPIO_IRQS; i++) {
795 if (bus_setup_intr(dev, sc->sc_res[i + 1],
796 INTR_TYPE_MISC | INTR_MPSAFE, bcm_gpio_intr,
797 NULL, sc, &sc->sc_intrhand[i]) != 0) {
806 bcm_gpio_intr_detach(device_t dev)
808 struct bcm_gpio_softc *sc;
811 sc = device_get_softc(dev);
812 for (i = 0; i < BCM_GPIO_IRQS; i++) {
813 if (sc->sc_intrhand[i]) {
814 bus_teardown_intr(dev, sc->sc_res[i + 1],
822 bcm_gpio_attach(device_t dev)
826 struct bcm_gpio_softc *sc;
829 if (bcm_gpio_sc != NULL)
832 bcm_gpio_sc = sc = device_get_softc(dev);
834 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN);
835 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) {
836 device_printf(dev, "cannot allocate resources\n");
839 sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
840 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
841 /* Setup the GPIO interrupt handler. */
842 if (bcm_gpio_intr_attach(dev)) {
843 device_printf(dev, "unable to setup the gpio irq handler\n");
847 gpio = ofw_bus_get_node(sc->sc_dev);
848 if (!OF_hasprop(gpio, "gpio-controller"))
849 /* Node is not a GPIO controller. */
852 * Find the read-only pins. These are pins we never touch or bad
853 * things could happen.
855 if (bcm_gpio_get_reserved_pins(sc) == -1)
857 /* Initialize the software controlled pins. */
858 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) {
859 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
861 func = bcm_gpio_get_function(sc, j);
862 sc->sc_gpio_pins[i].gp_pin = j;
863 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS;
864 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func);
866 /* The default is active-low interrupts. */
867 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
868 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
872 sc->sc_gpio_npins = i;
873 bcm_gpio_sysctl_init(sc);
874 sc->sc_busdev = gpiobus_attach_bus(dev);
875 if (sc->sc_busdev == NULL)
881 bcm_gpio_intr_detach(dev);
882 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res);
883 mtx_destroy(&sc->sc_mtx);
889 bcm_gpio_detach(device_t dev)
897 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
901 /* Write 1 to clear. */
902 bank = BCM_GPIO_BANK(bgi->bgi_irq);
903 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask);
907 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi)
911 bank = BCM_GPIO_BANK(bgi->bgi_irq);
912 return (bgi->bgi_reg == BCM_GPIO_GPHEN(bank) ||
913 bgi->bgi_reg == BCM_GPIO_GPLEN(bank));
917 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
921 BCM_GPIO_CLEAR_BITS(sc, bgi->bgi_reg, bgi->bgi_mask);
922 BCM_GPIO_UNLOCK(bcm_gpio_sc);
926 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
930 BCM_GPIO_SET_BITS(sc, bgi->bgi_reg, bgi->bgi_mask);
935 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank)
938 struct bcm_gpio_irqsrc *bgi;
941 /* Do not care of spurious interrupt on GPIO. */
942 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));
944 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1;
945 bgi = sc->sc_isrcs + irq;
946 if (!bcm_gpio_isrc_is_level(bgi))
947 bcm_gpio_isrc_eoi(sc, bgi);
948 if (intr_isrc_dispatch(&bgi->bgi_isrc,
949 curthread->td_intr_frame) != 0) {
950 bcm_gpio_isrc_mask(sc, bgi);
951 if (bcm_gpio_isrc_is_level(bgi))
952 bcm_gpio_isrc_eoi(sc, bgi);
953 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
956 reg &= ~bgi->bgi_mask;
958 return (FILTER_HANDLED);
962 bcm_gpio_intr_bank0(void *arg)
965 return (bcm_gpio_intr_internal(arg, 0));
969 bcm_gpio_intr_bank1(void *arg)
972 return (bcm_gpio_intr_internal(arg, 1));
976 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc)
982 name = device_get_nameunit(sc->sc_dev);
983 for (irq = 0; irq < BCM_GPIO_PINS; irq++) {
984 sc->sc_isrcs[irq].bgi_irq = irq;
985 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq);
986 sc->sc_isrcs[irq].bgi_reg = 0;
988 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc,
989 sc->sc_dev, 0, "%s,%u", name, irq);
991 return (error); /* XXX deregister ISRCs */
993 return (intr_pic_register(sc->sc_dev,
994 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))));
998 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc)
1002 * There has not been established any procedure yet
1003 * how to detach PIC from living system correctly.
1005 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
1010 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1012 struct bcm_gpio_softc *sc = device_get_softc(dev);
1013 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1015 bcm_gpio_isrc_mask(sc, bgi);
1019 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1021 struct bcm_gpio_softc *sc = device_get_softc(dev);
1022 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1024 arm_irq_memory_barrier(bgi->bgi_irq);
1025 bcm_gpio_isrc_unmask(sc, bgi);
1029 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, u_int ncells, pcell_t *cells,
1030 u_int *irqp, uint32_t *regp)
1036 * The first cell is the interrupt number.
1037 * The second cell is used to specify flags:
1038 * bits[3:0] trigger type and level flags:
1039 * 1 = low-to-high edge triggered.
1040 * 2 = high-to-low edge triggered.
1041 * 4 = active high level-sensitive.
1042 * 8 = active low level-sensitive.
1048 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq))
1052 * All interrupt types could be set for an interrupt at one moment.
1053 * At least, the combination of 'low-to-high' and 'high-to-low' edge
1054 * triggered interrupt types can make a sense. However, no combo is
1057 bank = BCM_GPIO_BANK(irq);
1059 reg = BCM_GPIO_GPREN(bank);
1060 else if (cells[1] == 2)
1061 reg = BCM_GPIO_GPFEN(bank);
1062 else if (cells[1] == 4)
1063 reg = BCM_GPIO_GPHEN(bank);
1064 else if (cells[1] == 8)
1065 reg = BCM_GPIO_GPLEN(bank);
1076 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1077 struct intr_irqsrc **isrcp)
1081 struct bcm_gpio_softc *sc;
1083 if (data->type != INTR_MAP_DATA_FDT)
1086 sc = device_get_softc(dev);
1087 error = bcm_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells,
1090 *isrcp = &sc->sc_isrcs[irq].bgi_isrc;
1095 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1097 struct bcm_gpio_softc *sc = device_get_softc(dev);
1098 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1100 if (bcm_gpio_isrc_is_level(bgi))
1101 bcm_gpio_isrc_eoi(sc, bgi);
1105 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1108 bcm_gpio_pic_enable_intr(dev, isrc);
1112 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1114 struct bcm_gpio_softc *sc = device_get_softc(dev);
1115 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1117 bcm_gpio_isrc_mask(sc, bgi);
1118 if (bcm_gpio_isrc_is_level(bgi))
1119 bcm_gpio_isrc_eoi(sc, bgi);
1123 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1124 struct resource *res, struct intr_map_data *data)
1128 struct bcm_gpio_softc *sc;
1129 struct bcm_gpio_irqsrc *bgi;
1131 if (data == NULL || data->type != INTR_MAP_DATA_FDT)
1134 sc = device_get_softc(dev);
1135 bgi = (struct bcm_gpio_irqsrc *)isrc;
1137 /* Get and check config for an interrupt. */
1138 if (bcm_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells, &irq,
1139 ®) != 0 || bgi->bgi_irq != irq)
1143 * If this is a setup for another handler,
1144 * only check that its configuration match.
1146 if (isrc->isrc_handlers != 0)
1147 return (bgi->bgi_reg == reg ? 0 : EINVAL);
1149 bank = BCM_GPIO_BANK(irq);
1151 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
1152 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
1153 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask);
1154 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask);
1156 BCM_GPIO_SET_BITS(sc, reg, bgi->bgi_mask);
1157 BCM_GPIO_UNLOCK(sc);
1162 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1163 struct resource *res, struct intr_map_data *data)
1165 struct bcm_gpio_softc *sc = device_get_softc(dev);
1166 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1168 if (isrc->isrc_handlers == 0) {
1170 BCM_GPIO_CLEAR_BITS(sc, bgi->bgi_reg, bgi->bgi_mask);
1172 BCM_GPIO_UNLOCK(sc);
1179 bcm_gpio_intr_reg(struct bcm_gpio_softc *sc, unsigned int irq, uint32_t bank)
1182 if (irq > BCM_GPIO_PINS)
1184 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) {
1185 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1186 return (BCM_GPIO_GPLEN(bank));
1187 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1188 return (BCM_GPIO_GPHEN(bank));
1189 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) {
1190 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1191 return (BCM_GPIO_GPFEN(bank));
1192 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1193 return (BCM_GPIO_GPREN(bank));
1200 bcm_gpio_mask_irq(void *source)
1202 uint32_t bank, mask, reg;
1205 irq = (unsigned int)source;
1206 if (irq > BCM_GPIO_PINS)
1208 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq))
1210 bank = BCM_GPIO_BANK(irq);
1211 mask = BCM_GPIO_MASK(irq);
1212 BCM_GPIO_LOCK(bcm_gpio_sc);
1213 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank);
1215 BCM_GPIO_CLEAR_BITS(bcm_gpio_sc, reg, mask);
1216 BCM_GPIO_UNLOCK(bcm_gpio_sc);
1220 bcm_gpio_unmask_irq(void *source)
1222 uint32_t bank, mask, reg;
1225 irq = (unsigned int)source;
1226 if (irq > BCM_GPIO_PINS)
1228 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq))
1230 bank = BCM_GPIO_BANK(irq);
1231 mask = BCM_GPIO_MASK(irq);
1232 BCM_GPIO_LOCK(bcm_gpio_sc);
1233 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank);
1235 BCM_GPIO_SET_BITS(bcm_gpio_sc, reg, mask);
1236 BCM_GPIO_UNLOCK(bcm_gpio_sc);
1240 bcm_gpio_activate_resource(device_t bus, device_t child, int type, int rid,
1241 struct resource *res)
1245 if (type != SYS_RES_IRQ)
1247 /* Unmask the interrupt. */
1248 pin = rman_get_start(res);
1249 bcm_gpio_unmask_irq((void *)pin);
1255 bcm_gpio_deactivate_resource(device_t bus, device_t child, int type, int rid,
1256 struct resource *res)
1260 if (type != SYS_RES_IRQ)
1262 /* Mask the interrupt. */
1263 pin = rman_get_start(res);
1264 bcm_gpio_mask_irq((void *)pin);
1270 bcm_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig,
1271 enum intr_polarity pol)
1274 struct bcm_gpio_softc *sc;
1275 uint32_t mask, oldreg, reg;
1277 if (irq > BCM_GPIO_PINS)
1279 /* There is no standard trigger or polarity. */
1280 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
1282 sc = device_get_softc(dev);
1283 if (bcm_gpio_pin_is_ro(sc, irq))
1285 bank = BCM_GPIO_BANK(irq);
1286 mask = BCM_GPIO_MASK(irq);
1288 oldreg = bcm_gpio_intr_reg(sc, irq, bank);
1289 sc->sc_irq_trigger[irq] = trig;
1290 sc->sc_irq_polarity[irq] = pol;
1291 reg = bcm_gpio_intr_reg(sc, irq, bank);
1293 BCM_GPIO_SET_BITS(sc, reg, mask);
1294 if (reg != oldreg && oldreg != 0)
1295 BCM_GPIO_CLEAR_BITS(sc, oldreg, mask);
1296 BCM_GPIO_UNLOCK(sc);
1302 bcm_gpio_setup_intr(device_t bus, device_t child, struct resource *ires,
1303 int flags, driver_filter_t *filt, driver_intr_t *handler,
1304 void *arg, void **cookiep)
1306 struct bcm_gpio_softc *sc;
1307 struct intr_event *event;
1310 sc = device_get_softc(bus);
1311 pin = rman_get_start(ires);
1312 if (pin > BCM_GPIO_PINS)
1313 panic("%s: bad pin %d", __func__, pin);
1314 event = sc->sc_events[pin];
1315 if (event == NULL) {
1316 error = intr_event_create(&event, (void *)pin, 0, pin,
1317 bcm_gpio_mask_irq, bcm_gpio_unmask_irq, NULL, NULL,
1318 "gpio%d pin%d:", device_get_unit(bus), pin);
1321 sc->sc_events[pin] = event;
1323 intr_event_add_handler(event, device_get_nameunit(child), filt,
1324 handler, arg, intr_priority(flags), flags, cookiep);
1330 bcm_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires,
1333 struct bcm_gpio_softc *sc;
1336 sc = device_get_softc(dev);
1337 pin = rman_get_start(ires);
1338 if (pin > BCM_GPIO_PINS)
1339 panic("%s: bad pin %d", __func__, pin);
1340 if (sc->sc_events[pin] == NULL)
1341 panic("Trying to teardown unoccupied IRQ");
1342 err = intr_event_remove_handler(cookie);
1344 sc->sc_events[pin] = NULL;
1351 bcm_gpio_get_node(device_t bus, device_t dev)
1354 /* We only have one child, the GPIO bus, which needs our own node. */
1355 return (ofw_bus_get_node(bus));
1358 static device_method_t bcm_gpio_methods[] = {
1359 /* Device interface */
1360 DEVMETHOD(device_probe, bcm_gpio_probe),
1361 DEVMETHOD(device_attach, bcm_gpio_attach),
1362 DEVMETHOD(device_detach, bcm_gpio_detach),
1365 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus),
1366 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max),
1367 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname),
1368 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags),
1369 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps),
1370 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags),
1371 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get),
1372 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set),
1373 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle),
1376 /* Interrupt controller interface */
1377 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr),
1378 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr),
1379 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr),
1380 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter),
1381 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread),
1382 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread),
1383 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr),
1384 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr),
1387 DEVMETHOD(bus_activate_resource, bcm_gpio_activate_resource),
1388 DEVMETHOD(bus_deactivate_resource, bcm_gpio_deactivate_resource),
1389 DEVMETHOD(bus_config_intr, bcm_gpio_config_intr),
1390 DEVMETHOD(bus_setup_intr, bcm_gpio_setup_intr),
1391 DEVMETHOD(bus_teardown_intr, bcm_gpio_teardown_intr),
1393 /* ofw_bus interface */
1394 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node),
1399 static devclass_t bcm_gpio_devclass;
1401 static driver_t bcm_gpio_driver = {
1404 sizeof(struct bcm_gpio_softc),
1407 DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0);