2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include "opt_platform.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/interrupt.h>
40 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
46 #include <sys/sysctl.h>
48 #include <machine/bus.h>
49 #include <machine/intr.h>
51 #include <dev/fdt/fdt_pinctrl.h>
52 #include <dev/gpio/gpiobusvar.h>
53 #include <dev/ofw/ofw_bus.h>
60 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
61 printf(fmt,##args); } while (0)
63 #define dprintf(fmt, args...)
66 #define BCM_GPIO_IRQS 4
67 #define BCM_GPIO_PINS 54
68 #define BCM_GPIO_PINS_PER_BANK 32
70 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
71 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \
72 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \
73 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
75 #define BCM2835_FSEL_GPIO_IN 0
76 #define BCM2835_FSEL_GPIO_OUT 1
77 #define BCM2835_FSEL_ALT5 2
78 #define BCM2835_FSEL_ALT4 3
79 #define BCM2835_FSEL_ALT0 4
80 #define BCM2835_FSEL_ALT1 5
81 #define BCM2835_FSEL_ALT2 6
82 #define BCM2835_FSEL_ALT3 7
84 #define BCM2835_PUD_OFF 0
85 #define BCM2835_PUD_DOWN 1
86 #define BCM2835_PUD_UP 2
88 static struct resource_spec bcm_gpio_res_spec[] = {
89 { SYS_RES_MEMORY, 0, RF_ACTIVE },
90 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */
91 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */
95 struct bcm_gpio_sysctl {
96 struct bcm_gpio_softc *sc;
100 struct bcm_gpio_irqsrc {
101 struct intr_irqsrc bgi_isrc;
107 struct bcm_gpio_softc {
111 struct resource * sc_res[BCM_GPIO_IRQS + 1];
112 bus_space_tag_t sc_bst;
113 bus_space_handle_t sc_bsh;
114 void * sc_intrhand[BCM_GPIO_IRQS];
117 int sc_ro_pins[BCM_GPIO_PINS];
118 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS];
119 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS];
120 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS];
129 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
130 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
131 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
132 #define BCM_GPIO_WRITE(_sc, _off, _val) \
133 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
134 #define BCM_GPIO_READ(_sc, _off) \
135 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
136 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \
137 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits))
138 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \
139 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits)
140 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK)
141 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK))
143 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */
144 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */
145 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */
146 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */
147 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */
148 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */
149 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */
150 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */
151 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */
152 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */
153 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */
154 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */
155 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */
157 static struct ofw_compat_data compat_data[] = {
158 {"broadcom,bcm2835-gpio", 1},
159 {"brcm,bcm2835-gpio", 1},
163 static struct bcm_gpio_softc *bcm_gpio_sc = NULL;
165 static int bcm_gpio_intr_bank0(void *arg);
166 static int bcm_gpio_intr_bank1(void *arg);
167 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc);
168 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc);
171 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin)
175 for (i = 0; i < sc->sc_ro_npins; i++)
176 if (pin == sc->sc_ro_pins[i])
182 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin)
184 uint32_t bank, func, offset;
186 /* Five banks, 10 pins per bank, 3 bits per pin. */
188 offset = (pin - bank * 10) * 3;
191 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7;
198 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize)
202 case BCM2835_FSEL_GPIO_IN:
203 strncpy(buf, "input", bufsize);
205 case BCM2835_FSEL_GPIO_OUT:
206 strncpy(buf, "output", bufsize);
208 case BCM2835_FSEL_ALT0:
209 strncpy(buf, "alt0", bufsize);
211 case BCM2835_FSEL_ALT1:
212 strncpy(buf, "alt1", bufsize);
214 case BCM2835_FSEL_ALT2:
215 strncpy(buf, "alt2", bufsize);
217 case BCM2835_FSEL_ALT3:
218 strncpy(buf, "alt3", bufsize);
220 case BCM2835_FSEL_ALT4:
221 strncpy(buf, "alt4", bufsize);
223 case BCM2835_FSEL_ALT5:
224 strncpy(buf, "alt5", bufsize);
227 strncpy(buf, "invalid", bufsize);
232 bcm_gpio_str_func(char *func, uint32_t *nfunc)
235 if (strcasecmp(func, "input") == 0)
236 *nfunc = BCM2835_FSEL_GPIO_IN;
237 else if (strcasecmp(func, "output") == 0)
238 *nfunc = BCM2835_FSEL_GPIO_OUT;
239 else if (strcasecmp(func, "alt0") == 0)
240 *nfunc = BCM2835_FSEL_ALT0;
241 else if (strcasecmp(func, "alt1") == 0)
242 *nfunc = BCM2835_FSEL_ALT1;
243 else if (strcasecmp(func, "alt2") == 0)
244 *nfunc = BCM2835_FSEL_ALT2;
245 else if (strcasecmp(func, "alt3") == 0)
246 *nfunc = BCM2835_FSEL_ALT3;
247 else if (strcasecmp(func, "alt4") == 0)
248 *nfunc = BCM2835_FSEL_ALT4;
249 else if (strcasecmp(func, "alt5") == 0)
250 *nfunc = BCM2835_FSEL_ALT5;
258 bcm_gpio_func_flag(uint32_t nfunc)
262 case BCM2835_FSEL_GPIO_IN:
263 return (GPIO_PIN_INPUT);
264 case BCM2835_FSEL_GPIO_OUT:
265 return (GPIO_PIN_OUTPUT);
271 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f)
273 uint32_t bank, data, offset;
275 /* Must be called with lock held. */
276 BCM_GPIO_LOCK_ASSERT(sc);
278 /* Five banks, 10 pins per bank, 3 bits per pin. */
280 offset = (pin - bank * 10) * 3;
282 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank));
283 data &= ~(7 << offset);
284 data |= (f << offset);
285 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data);
289 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state)
293 /* Must be called with lock held. */
294 BCM_GPIO_LOCK_ASSERT(sc);
296 bank = BCM_GPIO_BANK(pin);
297 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state);
298 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin));
299 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0);
300 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0);
304 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc)
306 struct bcm_gpio_softc *sc;
309 sc = device_get_softc(dev);
312 /* Set the pin function. */
313 bcm_gpio_set_function(sc, pin, nfunc);
315 /* Update the pin flags. */
316 for (i = 0; i < sc->sc_gpio_npins; i++) {
317 if (sc->sc_gpio_pins[i].gp_pin == pin)
320 if (i < sc->sc_gpio_npins)
321 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc);
327 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin,
334 * Manage input/output.
336 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
337 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
338 if (flags & GPIO_PIN_OUTPUT) {
339 pin->gp_flags |= GPIO_PIN_OUTPUT;
340 bcm_gpio_set_function(sc, pin->gp_pin,
341 BCM2835_FSEL_GPIO_OUT);
343 pin->gp_flags |= GPIO_PIN_INPUT;
344 bcm_gpio_set_function(sc, pin->gp_pin,
345 BCM2835_FSEL_GPIO_IN);
349 /* Manage Pull-up/pull-down. */
350 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
351 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
352 if (flags & GPIO_PIN_PULLUP) {
353 pin->gp_flags |= GPIO_PIN_PULLUP;
354 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP);
356 pin->gp_flags |= GPIO_PIN_PULLDOWN;
357 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN);
360 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE);
366 bcm_gpio_get_bus(device_t dev)
368 struct bcm_gpio_softc *sc;
370 sc = device_get_softc(dev);
372 return (sc->sc_busdev);
376 bcm_gpio_pin_max(device_t dev, int *maxpin)
379 *maxpin = BCM_GPIO_PINS - 1;
384 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
386 struct bcm_gpio_softc *sc = device_get_softc(dev);
389 for (i = 0; i < sc->sc_gpio_npins; i++) {
390 if (sc->sc_gpio_pins[i].gp_pin == pin)
394 if (i >= sc->sc_gpio_npins)
398 *caps = sc->sc_gpio_pins[i].gp_caps;
405 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
407 struct bcm_gpio_softc *sc = device_get_softc(dev);
410 for (i = 0; i < sc->sc_gpio_npins; i++) {
411 if (sc->sc_gpio_pins[i].gp_pin == pin)
415 if (i >= sc->sc_gpio_npins)
419 *flags = sc->sc_gpio_pins[i].gp_flags;
426 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
428 struct bcm_gpio_softc *sc = device_get_softc(dev);
431 for (i = 0; i < sc->sc_gpio_npins; i++) {
432 if (sc->sc_gpio_pins[i].gp_pin == pin)
436 if (i >= sc->sc_gpio_npins)
440 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
447 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
449 struct bcm_gpio_softc *sc = device_get_softc(dev);
452 for (i = 0; i < sc->sc_gpio_npins; i++) {
453 if (sc->sc_gpio_pins[i].gp_pin == pin)
457 if (i >= sc->sc_gpio_npins)
460 /* We never touch on read-only/reserved pins. */
461 if (bcm_gpio_pin_is_ro(sc, pin))
464 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
470 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
472 struct bcm_gpio_softc *sc = device_get_softc(dev);
476 for (i = 0; i < sc->sc_gpio_npins; i++) {
477 if (sc->sc_gpio_pins[i].gp_pin == pin)
480 if (i >= sc->sc_gpio_npins)
482 /* We never write to read-only/reserved pins. */
483 if (bcm_gpio_pin_is_ro(sc, pin))
486 bank = BCM_GPIO_BANK(pin);
488 reg = BCM_GPIO_GPSET(bank);
490 reg = BCM_GPIO_GPCLR(bank);
491 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
498 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
500 struct bcm_gpio_softc *sc = device_get_softc(dev);
501 uint32_t bank, reg_data;
504 for (i = 0; i < sc->sc_gpio_npins; i++) {
505 if (sc->sc_gpio_pins[i].gp_pin == pin)
508 if (i >= sc->sc_gpio_npins)
510 bank = BCM_GPIO_BANK(pin);
512 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
514 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0;
520 bcm_gpio_pin_toggle(device_t dev, uint32_t pin)
522 struct bcm_gpio_softc *sc = device_get_softc(dev);
523 uint32_t bank, data, reg;
526 for (i = 0; i < sc->sc_gpio_npins; i++) {
527 if (sc->sc_gpio_pins[i].gp_pin == pin)
530 if (i >= sc->sc_gpio_npins)
532 /* We never write to read-only/reserved pins. */
533 if (bcm_gpio_pin_is_ro(sc, pin))
536 bank = BCM_GPIO_BANK(pin);
537 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
538 if (data & BCM_GPIO_MASK(pin))
539 reg = BCM_GPIO_GPCLR(bank);
541 reg = BCM_GPIO_GPSET(bank);
542 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
549 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS)
552 struct bcm_gpio_softc *sc;
553 struct bcm_gpio_sysctl *sc_sysctl;
560 /* Get the current pin function. */
561 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin);
562 bcm_gpio_func_str(nfunc, buf, sizeof(buf));
564 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
565 if (error != 0 || req->newptr == NULL)
567 /* Ignore changes on read-only pins. */
568 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin))
570 /* Parse the user supplied string and check for a valid pin function. */
571 if (bcm_gpio_str_func(buf, &nfunc) != 0)
574 /* Update the pin alternate function. */
575 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc);
581 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc)
584 struct bcm_gpio_sysctl *sc_sysctl;
585 struct sysctl_ctx_list *ctx;
586 struct sysctl_oid *tree_node, *pin_node, *pinN_node;
587 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree;
591 * Add per-pin sysctl tree/handlers.
593 ctx = device_get_sysctl_ctx(sc->sc_dev);
594 tree_node = device_get_sysctl_tree(sc->sc_dev);
595 tree = SYSCTL_CHILDREN(tree_node);
596 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin",
597 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pins");
598 pin_tree = SYSCTL_CHILDREN(pin_node);
600 for (i = 0; i < sc->sc_gpio_npins; i++) {
602 snprintf(pinbuf, sizeof(pinbuf), "%d", i);
603 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf,
604 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GPIO Pin");
605 pinN_tree = SYSCTL_CHILDREN(pinN_node);
607 sc->sc_sysctl[i].sc = sc;
608 sc_sysctl = &sc->sc_sysctl[i];
610 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin;
611 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function",
612 CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, sc_sysctl,
613 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc,
614 "A", "Pin Function");
619 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node,
620 const char *propname, const char *label)
622 int i, need_comma, npins, range_start, range_stop;
625 /* Get the property data. */
626 npins = OF_getencprop_alloc_multi(node, propname, sizeof(*pins),
634 for (i = 0; i < npins; i++)
635 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i];
636 sc->sc_ro_npins += npins;
638 device_printf(sc->sc_dev, "%s pins: ", label);
639 range_start = range_stop = pins[0];
640 for (i = 1; i < npins; i++) {
641 if (pins[i] != range_stop + 1) {
644 if (range_start != range_stop)
645 printf("%d-%d", range_start, range_stop);
647 printf("%d", range_start);
648 range_start = range_stop = pins[i];
655 if (range_start != range_stop)
656 printf("%d-%d.\n", range_start, range_stop);
658 printf("%d.\n", range_start);
665 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc)
668 phandle_t gpio, node, reserved;
671 /* Get read-only pins if they're provided */
672 gpio = ofw_bus_get_node(sc->sc_dev);
673 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only",
676 /* Traverse the GPIO subnodes to find the reserved pins node. */
678 node = OF_child(gpio);
679 while ((node != 0) && (reserved == 0)) {
680 len = OF_getprop_alloc(node, "name", (void **)&name);
683 if (strcmp(name, "reserved") == 0)
686 node = OF_peer(node);
690 /* Get the reserved pins. */
691 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins",
699 bcm_gpio_probe(device_t dev)
702 if (!ofw_bus_status_okay(dev))
705 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
708 device_set_desc(dev, "BCM2708/2835 GPIO controller");
709 return (BUS_PROBE_DEFAULT);
713 bcm_gpio_intr_attach(device_t dev)
715 struct bcm_gpio_softc *sc;
718 * Only first two interrupt lines are used. Third line is
719 * mirrored second line and forth line is common for all banks.
721 sc = device_get_softc(dev);
722 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL)
725 if (bcm_gpio_pic_attach(sc) != 0) {
726 device_printf(dev, "unable to attach PIC\n");
729 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE,
730 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0)
732 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE,
733 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0)
740 bcm_gpio_intr_detach(device_t dev)
742 struct bcm_gpio_softc *sc;
744 sc = device_get_softc(dev);
745 if (sc->sc_intrhand[0] != NULL)
746 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]);
747 if (sc->sc_intrhand[1] != NULL)
748 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]);
750 bcm_gpio_pic_detach(sc);
754 bcm_gpio_attach(device_t dev)
758 struct bcm_gpio_softc *sc;
761 if (bcm_gpio_sc != NULL)
764 bcm_gpio_sc = sc = device_get_softc(dev);
766 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN);
767 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) {
768 device_printf(dev, "cannot allocate resources\n");
771 sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
772 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
773 /* Setup the GPIO interrupt handler. */
774 if (bcm_gpio_intr_attach(dev)) {
775 device_printf(dev, "unable to setup the gpio irq handler\n");
779 gpio = ofw_bus_get_node(sc->sc_dev);
780 if (!OF_hasprop(gpio, "gpio-controller"))
781 /* Node is not a GPIO controller. */
784 * Find the read-only pins. These are pins we never touch or bad
785 * things could happen.
787 if (bcm_gpio_get_reserved_pins(sc) == -1)
789 /* Initialize the software controlled pins. */
790 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) {
791 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
793 func = bcm_gpio_get_function(sc, j);
794 sc->sc_gpio_pins[i].gp_pin = j;
795 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS;
796 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func);
799 sc->sc_gpio_npins = i;
800 bcm_gpio_sysctl_init(sc);
801 sc->sc_busdev = gpiobus_attach_bus(dev);
802 if (sc->sc_busdev == NULL)
805 fdt_pinctrl_register(dev, "brcm,pins");
806 fdt_pinctrl_configure_tree(dev);
811 bcm_gpio_intr_detach(dev);
812 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res);
813 mtx_destroy(&sc->sc_mtx);
819 bcm_gpio_detach(device_t dev)
826 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask,
831 BCM_GPIO_SET_BITS(sc, reg, mask);
833 BCM_GPIO_CLEAR_BITS(sc, reg, mask);
837 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
841 /* Write 1 to clear. */
842 bank = BCM_GPIO_BANK(bgi->bgi_irq);
843 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask);
847 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi)
850 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW ||
851 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH);
855 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
859 bank = BCM_GPIO_BANK(bgi->bgi_irq);
861 switch (bgi->bgi_mode) {
862 case GPIO_INTR_LEVEL_LOW:
863 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask);
865 case GPIO_INTR_LEVEL_HIGH:
866 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask);
868 case GPIO_INTR_EDGE_RISING:
869 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
871 case GPIO_INTR_EDGE_FALLING:
872 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
874 case GPIO_INTR_EDGE_BOTH:
875 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
876 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
883 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
887 bank = BCM_GPIO_BANK(bgi->bgi_irq);
889 switch (bgi->bgi_mode) {
890 case GPIO_INTR_LEVEL_LOW:
891 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask);
893 case GPIO_INTR_LEVEL_HIGH:
894 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask);
896 case GPIO_INTR_EDGE_RISING:
897 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
899 case GPIO_INTR_EDGE_FALLING:
900 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
902 case GPIO_INTR_EDGE_BOTH:
903 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
904 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
911 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank)
914 struct bcm_gpio_irqsrc *bgi;
917 /* Do not care of spurious interrupt on GPIO. */
918 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));
920 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1;
921 bgi = sc->sc_isrcs + irq;
922 if (!bcm_gpio_isrc_is_level(bgi))
923 bcm_gpio_isrc_eoi(sc, bgi);
924 if (intr_isrc_dispatch(&bgi->bgi_isrc,
925 curthread->td_intr_frame) != 0) {
926 bcm_gpio_isrc_mask(sc, bgi);
927 if (bcm_gpio_isrc_is_level(bgi))
928 bcm_gpio_isrc_eoi(sc, bgi);
929 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
932 reg &= ~bgi->bgi_mask;
934 return (FILTER_HANDLED);
938 bcm_gpio_intr_bank0(void *arg)
941 return (bcm_gpio_intr_internal(arg, 0));
945 bcm_gpio_intr_bank1(void *arg)
948 return (bcm_gpio_intr_internal(arg, 1));
952 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc)
958 name = device_get_nameunit(sc->sc_dev);
959 for (irq = 0; irq < BCM_GPIO_PINS; irq++) {
960 sc->sc_isrcs[irq].bgi_irq = irq;
961 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq);
962 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM;
964 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc,
965 sc->sc_dev, 0, "%s,%u", name, irq);
967 return (error); /* XXX deregister ISRCs */
969 if (intr_pic_register(sc->sc_dev,
970 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL)
977 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc)
981 * There has not been established any procedure yet
982 * how to detach PIC from living system correctly.
984 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
989 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi,
994 bank = BCM_GPIO_BANK(bgi->bgi_irq);
996 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask,
997 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH);
998 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask,
999 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH);
1000 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask,
1001 mode == GPIO_INTR_LEVEL_HIGH);
1002 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask,
1003 mode == GPIO_INTR_LEVEL_LOW);
1004 bgi->bgi_mode = mode;
1005 BCM_GPIO_UNLOCK(sc);
1009 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1011 struct bcm_gpio_softc *sc = device_get_softc(dev);
1012 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1014 bcm_gpio_isrc_mask(sc, bgi);
1018 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1020 struct bcm_gpio_softc *sc = device_get_softc(dev);
1021 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1023 arm_irq_memory_barrier(bgi->bgi_irq);
1024 bcm_gpio_isrc_unmask(sc, bgi);
1028 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf,
1029 u_int *irqp, uint32_t *modep)
1035 * The first cell is the interrupt number.
1036 * The second cell is used to specify flags:
1037 * bits[3:0] trigger type and level flags:
1038 * 1 = low-to-high edge triggered.
1039 * 2 = high-to-low edge triggered.
1040 * 4 = active high level-sensitive.
1041 * 8 = active low level-sensitive.
1043 if (daf->ncells != 2)
1046 irq = daf->cells[0];
1047 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq))
1050 /* Only reasonable modes are supported. */
1051 if (daf->cells[1] == 1)
1052 mode = GPIO_INTR_EDGE_RISING;
1053 else if (daf->cells[1] == 2)
1054 mode = GPIO_INTR_EDGE_FALLING;
1055 else if (daf->cells[1] == 3)
1056 mode = GPIO_INTR_EDGE_BOTH;
1057 else if (daf->cells[1] == 4)
1058 mode = GPIO_INTR_LEVEL_HIGH;
1059 else if (daf->cells[1] == 8)
1060 mode = GPIO_INTR_LEVEL_LOW;
1071 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag,
1072 u_int *irqp, uint32_t *modep)
1077 irq = dag->gpio_pin_num;
1078 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq))
1081 mode = dag->gpio_intr_mode;
1082 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH &&
1083 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING &&
1084 mode != GPIO_INTR_EDGE_BOTH)
1094 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data,
1095 u_int *irqp, uint32_t *modep)
1098 switch (data->type) {
1099 case INTR_MAP_DATA_FDT:
1100 return (bcm_gpio_pic_map_fdt(sc,
1101 (struct intr_map_data_fdt *)data, irqp, modep));
1102 case INTR_MAP_DATA_GPIO:
1103 return (bcm_gpio_pic_map_gpio(sc,
1104 (struct intr_map_data_gpio *)data, irqp, modep));
1111 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1112 struct intr_irqsrc **isrcp)
1116 struct bcm_gpio_softc *sc = device_get_softc(dev);
1118 error = bcm_gpio_pic_map(sc, data, &irq, NULL);
1120 *isrcp = &sc->sc_isrcs[irq].bgi_isrc;
1125 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1127 struct bcm_gpio_softc *sc = device_get_softc(dev);
1128 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1130 if (bcm_gpio_isrc_is_level(bgi))
1131 bcm_gpio_isrc_eoi(sc, bgi);
1135 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1138 bcm_gpio_pic_enable_intr(dev, isrc);
1142 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1144 struct bcm_gpio_softc *sc = device_get_softc(dev);
1145 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1147 bcm_gpio_isrc_mask(sc, bgi);
1148 if (bcm_gpio_isrc_is_level(bgi))
1149 bcm_gpio_isrc_eoi(sc, bgi);
1153 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1154 struct resource *res, struct intr_map_data *data)
1158 struct bcm_gpio_softc *sc;
1159 struct bcm_gpio_irqsrc *bgi;
1164 sc = device_get_softc(dev);
1165 bgi = (struct bcm_gpio_irqsrc *)isrc;
1167 /* Get and check config for an interrupt. */
1168 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq)
1172 * If this is a setup for another handler,
1173 * only check that its configuration match.
1175 if (isrc->isrc_handlers != 0)
1176 return (bgi->bgi_mode == mode ? 0 : EINVAL);
1178 bcm_gpio_pic_config_intr(sc, bgi, mode);
1183 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1184 struct resource *res, struct intr_map_data *data)
1186 struct bcm_gpio_softc *sc = device_get_softc(dev);
1187 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1189 if (isrc->isrc_handlers == 0)
1190 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM);
1195 bcm_gpio_get_node(device_t bus, device_t dev)
1198 /* We only have one child, the GPIO bus, which needs our own node. */
1199 return (ofw_bus_get_node(bus));
1203 bcm_gpio_configure_pins(device_t dev, phandle_t cfgxref)
1206 int i, pintuples, pulltuples;
1211 static struct bcm_gpio_softc *sc;
1213 sc = device_get_softc(dev);
1214 cfgnode = OF_node_from_xref(cfgxref);
1217 pintuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pins",
1218 sizeof(*pins), (void **)&pins);
1221 OF_getprop(cfgnode, "name", &name, sizeof(name));
1227 return (0); /* Empty property is not an error. */
1229 if (OF_getencprop(cfgnode, "brcm,function", &function,
1230 sizeof(function)) <= 0) {
1236 pulltuples = OF_getencprop_alloc_multi(cfgnode, "brcm,pull",
1237 sizeof(*pulls), (void **)&pulls);
1239 if ((pulls != NULL) && (pulltuples != pintuples)) {
1241 OF_prop_free(pulls);
1245 for (i = 0; i < pintuples; i++) {
1247 bcm_gpio_set_alternate(dev, pin, function);
1249 device_printf(dev, "set pin %d to func %d", pin, function);
1252 printf(", pull %d", pulls[i]);
1254 /* Convert to gpio(4) flags */
1255 case BCM2835_PUD_OFF:
1256 bcm_gpio_pin_setflags(dev, pin, 0);
1258 case BCM2835_PUD_UP:
1259 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLUP);
1261 case BCM2835_PUD_DOWN:
1262 bcm_gpio_pin_setflags(dev, pin, GPIO_PIN_PULLDOWN);
1265 printf("%s: invalid pull value for pin %d: %d\n",
1266 name, pin, pulls[i]);
1275 OF_prop_free(pulls);
1280 static device_method_t bcm_gpio_methods[] = {
1281 /* Device interface */
1282 DEVMETHOD(device_probe, bcm_gpio_probe),
1283 DEVMETHOD(device_attach, bcm_gpio_attach),
1284 DEVMETHOD(device_detach, bcm_gpio_detach),
1287 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus),
1288 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max),
1289 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname),
1290 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags),
1291 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps),
1292 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags),
1293 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get),
1294 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set),
1295 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle),
1297 /* Interrupt controller interface */
1298 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr),
1299 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr),
1300 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr),
1301 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter),
1302 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread),
1303 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread),
1304 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr),
1305 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr),
1307 /* ofw_bus interface */
1308 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node),
1310 /* fdt_pinctrl interface */
1311 DEVMETHOD(fdt_pinctrl_configure, bcm_gpio_configure_pins),
1316 static devclass_t bcm_gpio_devclass;
1318 static driver_t bcm_gpio_driver = {
1321 sizeof(struct bcm_gpio_softc),
1324 EARLY_DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);