2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_platform.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <sys/sysctl.h>
46 #include <machine/bus.h>
47 #include <machine/intr.h>
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
52 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
61 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
62 printf(fmt,##args); } while (0)
64 #define dprintf(fmt, args...)
67 #define BCM_GPIO_IRQS 4
68 #define BCM_GPIO_PINS 54
69 #define BCM_GPIO_PINS_PER_BANK 32
72 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
73 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | \
74 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \
75 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
77 #define BCM_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
78 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
81 static struct resource_spec bcm_gpio_res_spec[] = {
82 { SYS_RES_MEMORY, 0, RF_ACTIVE },
83 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */
84 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */
85 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* bank 1 interrupt (mirrored) */
86 { SYS_RES_IRQ, 3, RF_ACTIVE }, /* bank 0-1 interrupt (united) */
90 struct bcm_gpio_sysctl {
91 struct bcm_gpio_softc *sc;
96 struct bcm_gpio_irqsrc {
97 struct intr_irqsrc bgi_isrc;
104 struct bcm_gpio_softc {
108 struct resource * sc_res[BCM_GPIO_IRQS + 1];
109 bus_space_tag_t sc_bst;
110 bus_space_handle_t sc_bsh;
111 void * sc_intrhand[BCM_GPIO_IRQS];
114 int sc_ro_pins[BCM_GPIO_PINS];
115 struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS];
117 struct intr_event * sc_events[BCM_GPIO_PINS];
119 struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS];
121 struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS];
123 enum intr_trigger sc_irq_trigger[BCM_GPIO_PINS];
124 enum intr_polarity sc_irq_polarity[BCM_GPIO_PINS];
134 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
135 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
136 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
137 #define BCM_GPIO_WRITE(_sc, _off, _val) \
138 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
139 #define BCM_GPIO_READ(_sc, _off) \
140 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
141 #define BCM_GPIO_CLEAR_BITS(_sc, _off, _bits) \
142 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) & ~(_bits))
143 #define BCM_GPIO_SET_BITS(_sc, _off, _bits) \
144 BCM_GPIO_WRITE(_sc, _off, BCM_GPIO_READ(_sc, _off) | _bits)
145 #define BCM_GPIO_BANK(a) (a / BCM_GPIO_PINS_PER_BANK)
146 #define BCM_GPIO_MASK(a) (1U << (a % BCM_GPIO_PINS_PER_BANK))
148 #define BCM_GPIO_GPFSEL(_bank) (0x00 + _bank * 4) /* Function Select */
149 #define BCM_GPIO_GPSET(_bank) (0x1c + _bank * 4) /* Pin Out Set */
150 #define BCM_GPIO_GPCLR(_bank) (0x28 + _bank * 4) /* Pin Out Clear */
151 #define BCM_GPIO_GPLEV(_bank) (0x34 + _bank * 4) /* Pin Level */
152 #define BCM_GPIO_GPEDS(_bank) (0x40 + _bank * 4) /* Event Status */
153 #define BCM_GPIO_GPREN(_bank) (0x4c + _bank * 4) /* Rising Edge irq */
154 #define BCM_GPIO_GPFEN(_bank) (0x58 + _bank * 4) /* Falling Edge irq */
155 #define BCM_GPIO_GPHEN(_bank) (0x64 + _bank * 4) /* High Level irq */
156 #define BCM_GPIO_GPLEN(_bank) (0x70 + _bank * 4) /* Low Level irq */
157 #define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */
158 #define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */
159 #define BCM_GPIO_GPPUD(_bank) (0x94) /* Pin Pull up/down */
160 #define BCM_GPIO_GPPUDCLK(_bank) (0x98 + _bank * 4) /* Pin Pull up clock */
162 static struct bcm_gpio_softc *bcm_gpio_sc = NULL;
165 static int bcm_gpio_intr_bank0(void *arg);
166 static int bcm_gpio_intr_bank1(void *arg);
167 static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc);
168 static int bcm_gpio_pic_detach(struct bcm_gpio_softc *sc);
172 bcm_gpio_pin_is_ro(struct bcm_gpio_softc *sc, int pin)
176 for (i = 0; i < sc->sc_ro_npins; i++)
177 if (pin == sc->sc_ro_pins[i])
183 bcm_gpio_get_function(struct bcm_gpio_softc *sc, uint32_t pin)
185 uint32_t bank, func, offset;
187 /* Five banks, 10 pins per bank, 3 bits per pin. */
189 offset = (pin - bank * 10) * 3;
192 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7;
199 bcm_gpio_func_str(uint32_t nfunc, char *buf, int bufsize)
204 strncpy(buf, "input", bufsize);
206 case BCM_GPIO_OUTPUT:
207 strncpy(buf, "output", bufsize);
210 strncpy(buf, "alt0", bufsize);
213 strncpy(buf, "alt1", bufsize);
216 strncpy(buf, "alt2", bufsize);
219 strncpy(buf, "alt3", bufsize);
222 strncpy(buf, "alt4", bufsize);
225 strncpy(buf, "alt5", bufsize);
228 strncpy(buf, "invalid", bufsize);
233 bcm_gpio_str_func(char *func, uint32_t *nfunc)
236 if (strcasecmp(func, "input") == 0)
237 *nfunc = BCM_GPIO_INPUT;
238 else if (strcasecmp(func, "output") == 0)
239 *nfunc = BCM_GPIO_OUTPUT;
240 else if (strcasecmp(func, "alt0") == 0)
241 *nfunc = BCM_GPIO_ALT0;
242 else if (strcasecmp(func, "alt1") == 0)
243 *nfunc = BCM_GPIO_ALT1;
244 else if (strcasecmp(func, "alt2") == 0)
245 *nfunc = BCM_GPIO_ALT2;
246 else if (strcasecmp(func, "alt3") == 0)
247 *nfunc = BCM_GPIO_ALT3;
248 else if (strcasecmp(func, "alt4") == 0)
249 *nfunc = BCM_GPIO_ALT4;
250 else if (strcasecmp(func, "alt5") == 0)
251 *nfunc = BCM_GPIO_ALT5;
259 bcm_gpio_func_flag(uint32_t nfunc)
264 return (GPIO_PIN_INPUT);
265 case BCM_GPIO_OUTPUT:
266 return (GPIO_PIN_OUTPUT);
272 bcm_gpio_set_function(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t f)
274 uint32_t bank, data, offset;
276 /* Must be called with lock held. */
277 BCM_GPIO_LOCK_ASSERT(sc);
279 /* Five banks, 10 pins per bank, 3 bits per pin. */
281 offset = (pin - bank * 10) * 3;
283 data = BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank));
284 data &= ~(7 << offset);
285 data |= (f << offset);
286 BCM_GPIO_WRITE(sc, BCM_GPIO_GPFSEL(bank), data);
290 bcm_gpio_set_pud(struct bcm_gpio_softc *sc, uint32_t pin, uint32_t state)
294 /* Must be called with lock held. */
295 BCM_GPIO_LOCK_ASSERT(sc);
297 bank = BCM_GPIO_BANK(pin);
298 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), state);
299 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), BCM_GPIO_MASK(pin));
300 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUD(0), 0);
301 BCM_GPIO_WRITE(sc, BCM_GPIO_GPPUDCLK(bank), 0);
305 bcm_gpio_set_alternate(device_t dev, uint32_t pin, uint32_t nfunc)
307 struct bcm_gpio_softc *sc;
310 sc = device_get_softc(dev);
313 /* Disable pull-up or pull-down on pin. */
314 bcm_gpio_set_pud(sc, pin, BCM_GPIO_NONE);
316 /* And now set the pin function. */
317 bcm_gpio_set_function(sc, pin, nfunc);
319 /* Update the pin flags. */
320 for (i = 0; i < sc->sc_gpio_npins; i++) {
321 if (sc->sc_gpio_pins[i].gp_pin == pin)
324 if (i < sc->sc_gpio_npins)
325 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(nfunc);
331 bcm_gpio_pin_configure(struct bcm_gpio_softc *sc, struct gpio_pin *pin,
338 * Manage input/output.
340 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
341 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
342 if (flags & GPIO_PIN_OUTPUT) {
343 pin->gp_flags |= GPIO_PIN_OUTPUT;
344 bcm_gpio_set_function(sc, pin->gp_pin,
347 pin->gp_flags |= GPIO_PIN_INPUT;
348 bcm_gpio_set_function(sc, pin->gp_pin,
353 /* Manage Pull-up/pull-down. */
354 pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
355 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
356 if (flags & GPIO_PIN_PULLUP) {
357 pin->gp_flags |= GPIO_PIN_PULLUP;
358 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLUP);
360 pin->gp_flags |= GPIO_PIN_PULLDOWN;
361 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_PULLDOWN);
364 bcm_gpio_set_pud(sc, pin->gp_pin, BCM_GPIO_NONE);
370 bcm_gpio_get_bus(device_t dev)
372 struct bcm_gpio_softc *sc;
374 sc = device_get_softc(dev);
376 return (sc->sc_busdev);
380 bcm_gpio_pin_max(device_t dev, int *maxpin)
383 *maxpin = BCM_GPIO_PINS - 1;
388 bcm_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
390 struct bcm_gpio_softc *sc = device_get_softc(dev);
393 for (i = 0; i < sc->sc_gpio_npins; i++) {
394 if (sc->sc_gpio_pins[i].gp_pin == pin)
398 if (i >= sc->sc_gpio_npins)
402 *caps = sc->sc_gpio_pins[i].gp_caps;
409 bcm_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
411 struct bcm_gpio_softc *sc = device_get_softc(dev);
414 for (i = 0; i < sc->sc_gpio_npins; i++) {
415 if (sc->sc_gpio_pins[i].gp_pin == pin)
419 if (i >= sc->sc_gpio_npins)
423 *flags = sc->sc_gpio_pins[i].gp_flags;
430 bcm_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
432 struct bcm_gpio_softc *sc = device_get_softc(dev);
435 for (i = 0; i < sc->sc_gpio_npins; i++) {
436 if (sc->sc_gpio_pins[i].gp_pin == pin)
440 if (i >= sc->sc_gpio_npins)
444 memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
451 bcm_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
453 struct bcm_gpio_softc *sc = device_get_softc(dev);
456 for (i = 0; i < sc->sc_gpio_npins; i++) {
457 if (sc->sc_gpio_pins[i].gp_pin == pin)
461 if (i >= sc->sc_gpio_npins)
464 /* We never touch on read-only/reserved pins. */
465 if (bcm_gpio_pin_is_ro(sc, pin))
468 bcm_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
474 bcm_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
476 struct bcm_gpio_softc *sc = device_get_softc(dev);
480 for (i = 0; i < sc->sc_gpio_npins; i++) {
481 if (sc->sc_gpio_pins[i].gp_pin == pin)
484 if (i >= sc->sc_gpio_npins)
486 /* We never write to read-only/reserved pins. */
487 if (bcm_gpio_pin_is_ro(sc, pin))
490 bank = BCM_GPIO_BANK(pin);
492 reg = BCM_GPIO_GPSET(bank);
494 reg = BCM_GPIO_GPCLR(bank);
495 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
502 bcm_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
504 struct bcm_gpio_softc *sc = device_get_softc(dev);
505 uint32_t bank, reg_data;
508 for (i = 0; i < sc->sc_gpio_npins; i++) {
509 if (sc->sc_gpio_pins[i].gp_pin == pin)
512 if (i >= sc->sc_gpio_npins)
514 bank = BCM_GPIO_BANK(pin);
516 reg_data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
518 *val = (reg_data & BCM_GPIO_MASK(pin)) ? 1 : 0;
524 bcm_gpio_pin_toggle(device_t dev, uint32_t pin)
526 struct bcm_gpio_softc *sc = device_get_softc(dev);
527 uint32_t bank, data, reg;
530 for (i = 0; i < sc->sc_gpio_npins; i++) {
531 if (sc->sc_gpio_pins[i].gp_pin == pin)
534 if (i >= sc->sc_gpio_npins)
536 /* We never write to read-only/reserved pins. */
537 if (bcm_gpio_pin_is_ro(sc, pin))
540 bank = BCM_GPIO_BANK(pin);
541 data = BCM_GPIO_READ(sc, BCM_GPIO_GPLEV(bank));
542 if (data & BCM_GPIO_MASK(pin))
543 reg = BCM_GPIO_GPCLR(bank);
545 reg = BCM_GPIO_GPSET(bank);
546 BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));
553 bcm_gpio_func_proc(SYSCTL_HANDLER_ARGS)
556 struct bcm_gpio_softc *sc;
557 struct bcm_gpio_sysctl *sc_sysctl;
564 /* Get the current pin function. */
565 nfunc = bcm_gpio_get_function(sc, sc_sysctl->pin);
566 bcm_gpio_func_str(nfunc, buf, sizeof(buf));
568 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
569 if (error != 0 || req->newptr == NULL)
571 /* Ignore changes on read-only pins. */
572 if (bcm_gpio_pin_is_ro(sc, sc_sysctl->pin))
574 /* Parse the user supplied string and check for a valid pin function. */
575 if (bcm_gpio_str_func(buf, &nfunc) != 0)
578 /* Update the pin alternate function. */
579 bcm_gpio_set_alternate(sc->sc_dev, sc_sysctl->pin, nfunc);
585 bcm_gpio_sysctl_init(struct bcm_gpio_softc *sc)
588 struct bcm_gpio_sysctl *sc_sysctl;
589 struct sysctl_ctx_list *ctx;
590 struct sysctl_oid *tree_node, *pin_node, *pinN_node;
591 struct sysctl_oid_list *tree, *pin_tree, *pinN_tree;
595 * Add per-pin sysctl tree/handlers.
597 ctx = device_get_sysctl_ctx(sc->sc_dev);
598 tree_node = device_get_sysctl_tree(sc->sc_dev);
599 tree = SYSCTL_CHILDREN(tree_node);
600 pin_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "pin",
601 CTLFLAG_RD, NULL, "GPIO Pins");
602 pin_tree = SYSCTL_CHILDREN(pin_node);
604 for (i = 0; i < sc->sc_gpio_npins; i++) {
606 snprintf(pinbuf, sizeof(pinbuf), "%d", i);
607 pinN_node = SYSCTL_ADD_NODE(ctx, pin_tree, OID_AUTO, pinbuf,
608 CTLFLAG_RD, NULL, "GPIO Pin");
609 pinN_tree = SYSCTL_CHILDREN(pinN_node);
611 sc->sc_sysctl[i].sc = sc;
612 sc_sysctl = &sc->sc_sysctl[i];
614 sc_sysctl->pin = sc->sc_gpio_pins[i].gp_pin;
615 SYSCTL_ADD_PROC(ctx, pinN_tree, OID_AUTO, "function",
616 CTLFLAG_RW | CTLTYPE_STRING, sc_sysctl,
617 sizeof(struct bcm_gpio_sysctl), bcm_gpio_func_proc,
618 "A", "Pin Function");
623 bcm_gpio_get_ro_pins(struct bcm_gpio_softc *sc, phandle_t node,
624 const char *propname, const char *label)
626 int i, need_comma, npins, range_start, range_stop;
629 /* Get the property data. */
630 npins = OF_getencprop_alloc(node, propname, sizeof(*pins),
638 for (i = 0; i < npins; i++)
639 sc->sc_ro_pins[i + sc->sc_ro_npins] = pins[i];
640 sc->sc_ro_npins += npins;
642 device_printf(sc->sc_dev, "%s pins: ", label);
643 range_start = range_stop = pins[0];
644 for (i = 1; i < npins; i++) {
645 if (pins[i] != range_stop + 1) {
648 if (range_start != range_stop)
649 printf("%d-%d", range_start, range_stop);
651 printf("%d", range_start);
652 range_start = range_stop = pins[i];
659 if (range_start != range_stop)
660 printf("%d-%d.\n", range_start, range_stop);
662 printf("%d.\n", range_start);
669 bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc)
672 phandle_t gpio, node, reserved;
675 /* Get read-only pins. */
676 gpio = ofw_bus_get_node(sc->sc_dev);
677 if (bcm_gpio_get_ro_pins(sc, gpio, "broadcom,read-only",
680 /* Traverse the GPIO subnodes to find the reserved pins node. */
682 node = OF_child(gpio);
683 while ((node != 0) && (reserved == 0)) {
684 len = OF_getprop_alloc(node, "name", 1, (void **)&name);
687 if (strcmp(name, "reserved") == 0)
690 node = OF_peer(node);
694 /* Get the reserved pins. */
695 if (bcm_gpio_get_ro_pins(sc, reserved, "broadcom,pins",
704 bcm_gpio_intr(void *arg)
707 struct bcm_gpio_softc *sc;
708 struct intr_event *event;
709 uint32_t bank, mask, reg;
711 sc = (struct bcm_gpio_softc *)arg;
714 for (irq = 0; irq < BCM_GPIO_PINS; irq++) {
715 bank = BCM_GPIO_BANK(irq);
716 mask = BCM_GPIO_MASK(irq);
717 if (bank != bank_last) {
718 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));
722 event = sc->sc_events[irq];
723 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
724 intr_event_handle(event, NULL);
726 device_printf(sc->sc_dev, "Stray IRQ %d\n",
729 /* Clear the Status bit by writing '1' to it. */
730 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), mask);
734 return (FILTER_HANDLED);
739 bcm_gpio_probe(device_t dev)
742 if (!ofw_bus_status_okay(dev))
745 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-gpio"))
748 device_set_desc(dev, "BCM2708/2835 GPIO controller");
749 return (BUS_PROBE_DEFAULT);
754 bcm_gpio_intr_attach(device_t dev)
756 struct bcm_gpio_softc *sc;
759 * Only first two interrupt lines are used. Third line is
760 * mirrored second line and forth line is common for all banks.
762 sc = device_get_softc(dev);
763 if (sc->sc_res[1] == NULL || sc->sc_res[2] == NULL)
766 if (bcm_gpio_pic_attach(sc) != 0) {
767 device_printf(dev, "unable to attach PIC\n");
770 if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_MISC | INTR_MPSAFE,
771 bcm_gpio_intr_bank0, NULL, sc, &sc->sc_intrhand[0]) != 0)
773 if (bus_setup_intr(dev, sc->sc_res[2], INTR_TYPE_MISC | INTR_MPSAFE,
774 bcm_gpio_intr_bank1, NULL, sc, &sc->sc_intrhand[1]) != 0)
781 bcm_gpio_intr_detach(device_t dev)
783 struct bcm_gpio_softc *sc;
785 sc = device_get_softc(dev);
786 if (sc->sc_intrhand[0] != NULL)
787 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_intrhand[0]);
788 if (sc->sc_intrhand[1] != NULL)
789 bus_teardown_intr(dev, sc->sc_res[2], sc->sc_intrhand[1]);
791 bcm_gpio_pic_detach(sc);
796 bcm_gpio_intr_attach(device_t dev)
798 struct bcm_gpio_softc *sc;
801 sc = device_get_softc(dev);
802 for (i = 0; i < BCM_GPIO_IRQS; i++) {
803 if (bus_setup_intr(dev, sc->sc_res[i + 1],
804 INTR_TYPE_MISC | INTR_MPSAFE, bcm_gpio_intr,
805 NULL, sc, &sc->sc_intrhand[i]) != 0) {
814 bcm_gpio_intr_detach(device_t dev)
816 struct bcm_gpio_softc *sc;
819 sc = device_get_softc(dev);
820 for (i = 0; i < BCM_GPIO_IRQS; i++) {
821 if (sc->sc_intrhand[i]) {
822 bus_teardown_intr(dev, sc->sc_res[i + 1],
830 bcm_gpio_attach(device_t dev)
834 struct bcm_gpio_softc *sc;
837 if (bcm_gpio_sc != NULL)
840 bcm_gpio_sc = sc = device_get_softc(dev);
842 mtx_init(&sc->sc_mtx, "bcm gpio", "gpio", MTX_SPIN);
843 if (bus_alloc_resources(dev, bcm_gpio_res_spec, sc->sc_res) != 0) {
844 device_printf(dev, "cannot allocate resources\n");
847 sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
848 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
849 /* Setup the GPIO interrupt handler. */
850 if (bcm_gpio_intr_attach(dev)) {
851 device_printf(dev, "unable to setup the gpio irq handler\n");
855 gpio = ofw_bus_get_node(sc->sc_dev);
856 if (!OF_hasprop(gpio, "gpio-controller"))
857 /* Node is not a GPIO controller. */
860 * Find the read-only pins. These are pins we never touch or bad
861 * things could happen.
863 if (bcm_gpio_get_reserved_pins(sc) == -1)
865 /* Initialize the software controlled pins. */
866 for (i = 0, j = 0; j < BCM_GPIO_PINS; j++) {
867 snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
869 func = bcm_gpio_get_function(sc, j);
870 sc->sc_gpio_pins[i].gp_pin = j;
871 sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS;
872 sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func);
874 /* The default is active-low interrupts. */
875 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
876 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
880 sc->sc_gpio_npins = i;
881 bcm_gpio_sysctl_init(sc);
882 sc->sc_busdev = gpiobus_attach_bus(dev);
883 if (sc->sc_busdev == NULL)
889 bcm_gpio_intr_detach(dev);
890 bus_release_resources(dev, bcm_gpio_res_spec, sc->sc_res);
891 mtx_destroy(&sc->sc_mtx);
897 bcm_gpio_detach(device_t dev)
905 bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask,
910 BCM_GPIO_SET_BITS(sc, reg, mask);
912 BCM_GPIO_CLEAR_BITS(sc, reg, mask);
916 bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
920 /* Write 1 to clear. */
921 bank = BCM_GPIO_BANK(bgi->bgi_irq);
922 BCM_GPIO_WRITE(sc, BCM_GPIO_GPEDS(bank), bgi->bgi_mask);
926 bcm_gpio_isrc_is_level(struct bcm_gpio_irqsrc *bgi)
929 return (bgi->bgi_mode == GPIO_INTR_LEVEL_LOW ||
930 bgi->bgi_mode == GPIO_INTR_LEVEL_HIGH);
934 bcm_gpio_isrc_mask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
938 bank = BCM_GPIO_BANK(bgi->bgi_irq);
940 switch (bgi->bgi_mode) {
941 case GPIO_INTR_LEVEL_LOW:
942 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask);
944 case GPIO_INTR_LEVEL_HIGH:
945 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask);
947 case GPIO_INTR_EDGE_RISING:
948 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
950 case GPIO_INTR_EDGE_FALLING:
951 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
953 case GPIO_INTR_EDGE_BOTH:
954 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
955 BCM_GPIO_CLEAR_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
962 bcm_gpio_isrc_unmask(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
966 bank = BCM_GPIO_BANK(bgi->bgi_irq);
968 switch (bgi->bgi_mode) {
969 case GPIO_INTR_LEVEL_LOW:
970 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask);
972 case GPIO_INTR_LEVEL_HIGH:
973 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask);
975 case GPIO_INTR_EDGE_RISING:
976 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
978 case GPIO_INTR_EDGE_FALLING:
979 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
981 case GPIO_INTR_EDGE_BOTH:
982 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask);
983 BCM_GPIO_SET_BITS(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask);
990 bcm_gpio_intr_internal(struct bcm_gpio_softc *sc, uint32_t bank)
993 struct bcm_gpio_irqsrc *bgi;
996 /* Do not care of spurious interrupt on GPIO. */
997 reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));
999 irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1;
1000 bgi = sc->sc_isrcs + irq;
1001 if (!bcm_gpio_isrc_is_level(bgi))
1002 bcm_gpio_isrc_eoi(sc, bgi);
1003 if (intr_isrc_dispatch(&bgi->bgi_isrc,
1004 curthread->td_intr_frame) != 0) {
1005 bcm_gpio_isrc_mask(sc, bgi);
1006 if (bcm_gpio_isrc_is_level(bgi))
1007 bcm_gpio_isrc_eoi(sc, bgi);
1008 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
1011 reg &= ~bgi->bgi_mask;
1013 return (FILTER_HANDLED);
1017 bcm_gpio_intr_bank0(void *arg)
1020 return (bcm_gpio_intr_internal(arg, 0));
1024 bcm_gpio_intr_bank1(void *arg)
1027 return (bcm_gpio_intr_internal(arg, 1));
1031 bcm_gpio_pic_attach(struct bcm_gpio_softc *sc)
1037 name = device_get_nameunit(sc->sc_dev);
1038 for (irq = 0; irq < BCM_GPIO_PINS; irq++) {
1039 sc->sc_isrcs[irq].bgi_irq = irq;
1040 sc->sc_isrcs[irq].bgi_mask = BCM_GPIO_MASK(irq);
1041 sc->sc_isrcs[irq].bgi_mode = GPIO_INTR_CONFORM;
1043 error = intr_isrc_register(&sc->sc_isrcs[irq].bgi_isrc,
1044 sc->sc_dev, 0, "%s,%u", name, irq);
1046 return (error); /* XXX deregister ISRCs */
1048 return (intr_pic_register(sc->sc_dev,
1049 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))));
1053 bcm_gpio_pic_detach(struct bcm_gpio_softc *sc)
1057 * There has not been established any procedure yet
1058 * how to detach PIC from living system correctly.
1060 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
1065 bcm_gpio_pic_config_intr(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi,
1070 bank = BCM_GPIO_BANK(bgi->bgi_irq);
1072 bcm_gpio_modify(sc, BCM_GPIO_GPREN(bank), bgi->bgi_mask,
1073 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH);
1074 bcm_gpio_modify(sc, BCM_GPIO_GPFEN(bank), bgi->bgi_mask,
1075 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH);
1076 bcm_gpio_modify(sc, BCM_GPIO_GPHEN(bank), bgi->bgi_mask,
1077 mode == GPIO_INTR_LEVEL_HIGH);
1078 bcm_gpio_modify(sc, BCM_GPIO_GPLEN(bank), bgi->bgi_mask,
1079 mode == GPIO_INTR_LEVEL_LOW);
1080 bgi->bgi_mode = mode;
1081 BCM_GPIO_UNLOCK(sc);
1085 bcm_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1087 struct bcm_gpio_softc *sc = device_get_softc(dev);
1088 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1090 bcm_gpio_isrc_mask(sc, bgi);
1094 bcm_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1096 struct bcm_gpio_softc *sc = device_get_softc(dev);
1097 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1099 arm_irq_memory_barrier(bgi->bgi_irq);
1100 bcm_gpio_isrc_unmask(sc, bgi);
1104 bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf,
1105 u_int *irqp, uint32_t *modep)
1108 uint32_t mode, bank;
1111 * The first cell is the interrupt number.
1112 * The second cell is used to specify flags:
1113 * bits[3:0] trigger type and level flags:
1114 * 1 = low-to-high edge triggered.
1115 * 2 = high-to-low edge triggered.
1116 * 4 = active high level-sensitive.
1117 * 8 = active low level-sensitive.
1119 if (daf->ncells != 2)
1122 irq = daf->cells[0];
1123 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq))
1126 /* Only reasonable modes are supported. */
1127 bank = BCM_GPIO_BANK(irq);
1128 if (daf->cells[1] == 1)
1129 mode = GPIO_INTR_EDGE_RISING;
1130 else if (daf->cells[1] == 2)
1131 mode = GPIO_INTR_EDGE_FALLING;
1132 else if (daf->cells[1] == 3)
1133 mode = GPIO_INTR_EDGE_BOTH;
1134 else if (daf->cells[1] == 4)
1135 mode = GPIO_INTR_LEVEL_HIGH;
1136 else if (daf->cells[1] == 8)
1137 mode = GPIO_INTR_LEVEL_LOW;
1148 bcm_gpio_pic_map_gpio(struct bcm_gpio_softc *sc, struct intr_map_data_gpio *dag,
1149 u_int *irqp, uint32_t *modep)
1154 irq = dag->gpio_pin_num;
1155 if (irq >= BCM_GPIO_PINS || bcm_gpio_pin_is_ro(sc, irq))
1158 mode = dag->gpio_intr_mode;
1159 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH &&
1160 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING &&
1161 mode != GPIO_INTR_EDGE_BOTH)
1171 bcm_gpio_pic_map(struct bcm_gpio_softc *sc, struct intr_map_data *data,
1172 u_int *irqp, uint32_t *modep)
1175 switch (data->type) {
1176 case INTR_MAP_DATA_FDT:
1177 return (bcm_gpio_pic_map_fdt(sc,
1178 (struct intr_map_data_fdt *)data, irqp, modep));
1179 case INTR_MAP_DATA_GPIO:
1180 return (bcm_gpio_pic_map_gpio(sc,
1181 (struct intr_map_data_gpio *)data, irqp, modep));
1188 bcm_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1189 struct intr_irqsrc **isrcp)
1193 struct bcm_gpio_softc *sc = device_get_softc(dev);
1195 error = bcm_gpio_pic_map(sc, data, &irq, NULL);
1197 *isrcp = &sc->sc_isrcs[irq].bgi_isrc;
1202 bcm_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1204 struct bcm_gpio_softc *sc = device_get_softc(dev);
1205 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1207 if (bcm_gpio_isrc_is_level(bgi))
1208 bcm_gpio_isrc_eoi(sc, bgi);
1212 bcm_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1215 bcm_gpio_pic_enable_intr(dev, isrc);
1219 bcm_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1221 struct bcm_gpio_softc *sc = device_get_softc(dev);
1222 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1224 bcm_gpio_isrc_mask(sc, bgi);
1225 if (bcm_gpio_isrc_is_level(bgi))
1226 bcm_gpio_isrc_eoi(sc, bgi);
1230 bcm_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1231 struct resource *res, struct intr_map_data *data)
1235 struct bcm_gpio_softc *sc;
1236 struct bcm_gpio_irqsrc *bgi;
1241 sc = device_get_softc(dev);
1242 bgi = (struct bcm_gpio_irqsrc *)isrc;
1244 /* Get and check config for an interrupt. */
1245 if (bcm_gpio_pic_map(sc, data, &irq, &mode) != 0 || bgi->bgi_irq != irq)
1249 * If this is a setup for another handler,
1250 * only check that its configuration match.
1252 if (isrc->isrc_handlers != 0)
1253 return (bgi->bgi_mode == mode ? 0 : EINVAL);
1255 bcm_gpio_pic_config_intr(sc, bgi, mode);
1260 bcm_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1261 struct resource *res, struct intr_map_data *data)
1263 struct bcm_gpio_softc *sc = device_get_softc(dev);
1264 struct bcm_gpio_irqsrc *bgi = (struct bcm_gpio_irqsrc *)isrc;
1266 if (isrc->isrc_handlers == 0)
1267 bcm_gpio_pic_config_intr(sc, bgi, GPIO_INTR_CONFORM);
1273 bcm_gpio_intr_reg(struct bcm_gpio_softc *sc, unsigned int irq, uint32_t bank)
1276 if (irq > BCM_GPIO_PINS)
1278 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) {
1279 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1280 return (BCM_GPIO_GPLEN(bank));
1281 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1282 return (BCM_GPIO_GPHEN(bank));
1283 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) {
1284 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
1285 return (BCM_GPIO_GPFEN(bank));
1286 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
1287 return (BCM_GPIO_GPREN(bank));
1294 bcm_gpio_mask_irq(void *source)
1296 uint32_t bank, mask, reg;
1299 irq = (unsigned int)source;
1300 if (irq > BCM_GPIO_PINS)
1302 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq))
1304 bank = BCM_GPIO_BANK(irq);
1305 mask = BCM_GPIO_MASK(irq);
1306 BCM_GPIO_LOCK(bcm_gpio_sc);
1307 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank);
1309 BCM_GPIO_CLEAR_BITS(bcm_gpio_sc, reg, mask);
1310 BCM_GPIO_UNLOCK(bcm_gpio_sc);
1314 bcm_gpio_unmask_irq(void *source)
1316 uint32_t bank, mask, reg;
1319 irq = (unsigned int)source;
1320 if (irq > BCM_GPIO_PINS)
1322 if (bcm_gpio_pin_is_ro(bcm_gpio_sc, irq))
1324 bank = BCM_GPIO_BANK(irq);
1325 mask = BCM_GPIO_MASK(irq);
1326 BCM_GPIO_LOCK(bcm_gpio_sc);
1327 reg = bcm_gpio_intr_reg(bcm_gpio_sc, irq, bank);
1329 BCM_GPIO_SET_BITS(bcm_gpio_sc, reg, mask);
1330 BCM_GPIO_UNLOCK(bcm_gpio_sc);
1334 bcm_gpio_activate_resource(device_t bus, device_t child, int type, int rid,
1335 struct resource *res)
1339 if (type != SYS_RES_IRQ)
1341 /* Unmask the interrupt. */
1342 pin = rman_get_start(res);
1343 bcm_gpio_unmask_irq((void *)pin);
1349 bcm_gpio_deactivate_resource(device_t bus, device_t child, int type, int rid,
1350 struct resource *res)
1354 if (type != SYS_RES_IRQ)
1356 /* Mask the interrupt. */
1357 pin = rman_get_start(res);
1358 bcm_gpio_mask_irq((void *)pin);
1364 bcm_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig,
1365 enum intr_polarity pol)
1368 struct bcm_gpio_softc *sc;
1369 uint32_t mask, oldreg, reg;
1371 if (irq > BCM_GPIO_PINS)
1373 /* There is no standard trigger or polarity. */
1374 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
1376 sc = device_get_softc(dev);
1377 if (bcm_gpio_pin_is_ro(sc, irq))
1379 bank = BCM_GPIO_BANK(irq);
1380 mask = BCM_GPIO_MASK(irq);
1382 oldreg = bcm_gpio_intr_reg(sc, irq, bank);
1383 sc->sc_irq_trigger[irq] = trig;
1384 sc->sc_irq_polarity[irq] = pol;
1385 reg = bcm_gpio_intr_reg(sc, irq, bank);
1387 BCM_GPIO_SET_BITS(sc, reg, mask);
1388 if (reg != oldreg && oldreg != 0)
1389 BCM_GPIO_CLEAR_BITS(sc, oldreg, mask);
1390 BCM_GPIO_UNLOCK(sc);
1396 bcm_gpio_setup_intr(device_t bus, device_t child, struct resource *ires,
1397 int flags, driver_filter_t *filt, driver_intr_t *handler,
1398 void *arg, void **cookiep)
1400 struct bcm_gpio_softc *sc;
1401 struct intr_event *event;
1404 sc = device_get_softc(bus);
1405 pin = rman_get_start(ires);
1406 if (pin > BCM_GPIO_PINS)
1407 panic("%s: bad pin %d", __func__, pin);
1408 event = sc->sc_events[pin];
1409 if (event == NULL) {
1410 error = intr_event_create(&event, (void *)pin, 0, pin,
1411 bcm_gpio_mask_irq, bcm_gpio_unmask_irq, NULL, NULL,
1412 "gpio%d pin%d:", device_get_unit(bus), pin);
1415 sc->sc_events[pin] = event;
1417 intr_event_add_handler(event, device_get_nameunit(child), filt,
1418 handler, arg, intr_priority(flags), flags, cookiep);
1424 bcm_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires,
1427 struct bcm_gpio_softc *sc;
1430 sc = device_get_softc(dev);
1431 pin = rman_get_start(ires);
1432 if (pin > BCM_GPIO_PINS)
1433 panic("%s: bad pin %d", __func__, pin);
1434 if (sc->sc_events[pin] == NULL)
1435 panic("Trying to teardown unoccupied IRQ");
1436 err = intr_event_remove_handler(cookie);
1438 sc->sc_events[pin] = NULL;
1445 bcm_gpio_get_node(device_t bus, device_t dev)
1448 /* We only have one child, the GPIO bus, which needs our own node. */
1449 return (ofw_bus_get_node(bus));
1452 static device_method_t bcm_gpio_methods[] = {
1453 /* Device interface */
1454 DEVMETHOD(device_probe, bcm_gpio_probe),
1455 DEVMETHOD(device_attach, bcm_gpio_attach),
1456 DEVMETHOD(device_detach, bcm_gpio_detach),
1459 DEVMETHOD(gpio_get_bus, bcm_gpio_get_bus),
1460 DEVMETHOD(gpio_pin_max, bcm_gpio_pin_max),
1461 DEVMETHOD(gpio_pin_getname, bcm_gpio_pin_getname),
1462 DEVMETHOD(gpio_pin_getflags, bcm_gpio_pin_getflags),
1463 DEVMETHOD(gpio_pin_getcaps, bcm_gpio_pin_getcaps),
1464 DEVMETHOD(gpio_pin_setflags, bcm_gpio_pin_setflags),
1465 DEVMETHOD(gpio_pin_get, bcm_gpio_pin_get),
1466 DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set),
1467 DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle),
1470 /* Interrupt controller interface */
1471 DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr),
1472 DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr),
1473 DEVMETHOD(pic_map_intr, bcm_gpio_pic_map_intr),
1474 DEVMETHOD(pic_post_filter, bcm_gpio_pic_post_filter),
1475 DEVMETHOD(pic_post_ithread, bcm_gpio_pic_post_ithread),
1476 DEVMETHOD(pic_pre_ithread, bcm_gpio_pic_pre_ithread),
1477 DEVMETHOD(pic_setup_intr, bcm_gpio_pic_setup_intr),
1478 DEVMETHOD(pic_teardown_intr, bcm_gpio_pic_teardown_intr),
1481 DEVMETHOD(bus_activate_resource, bcm_gpio_activate_resource),
1482 DEVMETHOD(bus_deactivate_resource, bcm_gpio_deactivate_resource),
1483 DEVMETHOD(bus_config_intr, bcm_gpio_config_intr),
1484 DEVMETHOD(bus_setup_intr, bcm_gpio_setup_intr),
1485 DEVMETHOD(bus_teardown_intr, bcm_gpio_teardown_intr),
1487 /* ofw_bus interface */
1488 DEVMETHOD(ofw_bus_get_node, bcm_gpio_get_node),
1493 static devclass_t bcm_gpio_devclass;
1495 static driver_t bcm_gpio_driver = {
1498 sizeof(struct bcm_gpio_softc),
1501 DRIVER_MODULE(bcm_gpio, simplebus, bcm_gpio_driver, bcm_gpio_devclass, 0, 0);