2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Based on OMAP3 INTC code by Ben Gray
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include "opt_platform.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
43 #include <machine/bus.h>
44 #include <machine/intr.h>
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
52 #define INTC_PENDING_BASIC 0x00
53 #define INTC_PENDING_BANK1 0x04
54 #define INTC_PENDING_BANK2 0x08
55 #define INTC_FIQ_CONTROL 0x0C
56 #define INTC_ENABLE_BANK1 0x10
57 #define INTC_ENABLE_BANK2 0x14
58 #define INTC_ENABLE_BASIC 0x18
59 #define INTC_DISABLE_BANK1 0x1C
60 #define INTC_DISABLE_BANK2 0x20
61 #define INTC_DISABLE_BASIC 0x24
63 #define INTC_PENDING_BASIC_ARM 0x0000FF
64 #define INTC_PENDING_BASIC_GPU1_PEND 0x000100
65 #define INTC_PENDING_BASIC_GPU2_PEND 0x000200
66 #define INTC_PENDING_BASIC_GPU1_7 0x000400
67 #define INTC_PENDING_BASIC_GPU1_9 0x000800
68 #define INTC_PENDING_BASIC_GPU1_10 0x001000
69 #define INTC_PENDING_BASIC_GPU1_18 0x002000
70 #define INTC_PENDING_BASIC_GPU1_19 0x004000
71 #define INTC_PENDING_BASIC_GPU2_21 0x008000
72 #define INTC_PENDING_BASIC_GPU2_22 0x010000
73 #define INTC_PENDING_BASIC_GPU2_23 0x020000
74 #define INTC_PENDING_BASIC_GPU2_24 0x040000
75 #define INTC_PENDING_BASIC_GPU2_25 0x080000
76 #define INTC_PENDING_BASIC_GPU2_30 0x100000
77 #define INTC_PENDING_BASIC_MASK 0x1FFFFF
79 #define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \
80 INTC_PENDING_BASIC_GPU1_9 | \
81 INTC_PENDING_BASIC_GPU1_10 | \
82 INTC_PENDING_BASIC_GPU1_18 | \
83 INTC_PENDING_BASIC_GPU1_19)
85 #define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \
86 INTC_PENDING_BASIC_GPU2_22 | \
87 INTC_PENDING_BASIC_GPU2_23 | \
88 INTC_PENDING_BASIC_GPU2_24 | \
89 INTC_PENDING_BASIC_GPU2_25 | \
90 INTC_PENDING_BASIC_GPU2_30)
92 #define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \
93 (1 << 18) | (1 << 19)))
94 #define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \
95 (1 << 24) | (1 << 25) | (1 << 30)))
98 #define BANK1_END (BANK1_START + 32 - 1)
99 #define BANK2_START (BANK1_START + 32)
100 #define BANK2_END (BANK2_START + 32 - 1)
102 #define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START))
103 #define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END))
104 #define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END))
105 #define IRQ_BANK1(n) ((n) - BANK1_START)
106 #define IRQ_BANK2(n) ((n) - BANK2_START)
109 #define dprintf(fmt, args...) printf(fmt, ##args)
111 #define dprintf(fmt, args...)
114 #define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */
116 struct bcm_intc_irqsrc {
117 struct intr_irqsrc bii_isrc;
119 uint16_t bii_disable_reg;
120 uint16_t bii_enable_reg;
124 struct bcm_intc_softc {
126 struct resource * intc_res;
127 bus_space_tag_t intc_bst;
128 bus_space_handle_t intc_bsh;
129 struct resource * intc_irq_res;
131 struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS];
134 static struct bcm_intc_softc *bcm_intc_sc = NULL;
136 #define intc_read_4(_sc, reg) \
137 bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg))
138 #define intc_write_4(_sc, reg, val) \
139 bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val))
142 bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
145 intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask);
149 bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
152 intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask);
156 bcm2835_intc_active_intr(struct bcm_intc_softc *sc)
158 uint32_t pending, pending_gpu;
160 pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK;
163 if (pending & INTC_PENDING_BASIC_ARM)
164 return (ffs(pending) - 1);
165 if (pending & INTC_PENDING_BASIC_GPU1_MASK) {
166 if (pending & INTC_PENDING_BASIC_GPU1_7)
167 return (BANK1_START + 7);
168 if (pending & INTC_PENDING_BASIC_GPU1_9)
169 return (BANK1_START + 9);
170 if (pending & INTC_PENDING_BASIC_GPU1_10)
171 return (BANK1_START + 10);
172 if (pending & INTC_PENDING_BASIC_GPU1_18)
173 return (BANK1_START + 18);
174 if (pending & INTC_PENDING_BASIC_GPU1_19)
175 return (BANK1_START + 19);
177 if (pending & INTC_PENDING_BASIC_GPU2_MASK) {
178 if (pending & INTC_PENDING_BASIC_GPU2_21)
179 return (BANK2_START + 21);
180 if (pending & INTC_PENDING_BASIC_GPU2_22)
181 return (BANK2_START + 22);
182 if (pending & INTC_PENDING_BASIC_GPU2_23)
183 return (BANK2_START + 23);
184 if (pending & INTC_PENDING_BASIC_GPU2_24)
185 return (BANK2_START + 24);
186 if (pending & INTC_PENDING_BASIC_GPU2_25)
187 return (BANK2_START + 25);
188 if (pending & INTC_PENDING_BASIC_GPU2_30)
189 return (BANK2_START + 30);
191 if (pending & INTC_PENDING_BASIC_GPU1_PEND) {
192 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1);
193 pending_gpu &= INTC_PENDING_BANK1_MASK;
194 if (pending_gpu != 0)
195 return (BANK1_START + ffs(pending_gpu) - 1);
197 if (pending & INTC_PENDING_BASIC_GPU2_PEND) {
198 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2);
199 pending_gpu &= INTC_PENDING_BANK2_MASK;
200 if (pending_gpu != 0)
201 return (BANK2_START + ffs(pending_gpu) - 1);
203 return (-1); /* It shouldn't end here, but it's hardware. */
207 bcm2835_intc_intr(void *arg)
210 struct bcm_intc_softc *sc = arg;
212 for (num = 0; ; num++) {
213 irq = bcm2835_intc_active_intr(sc);
216 if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc,
217 curthread->td_intr_frame) != 0) {
218 bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]);
219 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
222 arm_irq_memory_barrier(0); /* XXX */
225 device_printf(sc->sc_dev, "Spurious interrupt detected\n");
227 return (FILTER_HANDLED);
231 bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
233 struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc;
235 arm_irq_memory_barrier(bii->bii_irq);
236 bcm_intc_isrc_unmask(device_get_softc(dev), bii);
240 bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
243 bcm_intc_isrc_mask(device_get_softc(dev),
244 (struct bcm_intc_irqsrc *)isrc);
248 bcm_intc_map_intr(device_t dev, struct intr_map_data *data,
249 struct intr_irqsrc **isrcp)
252 struct intr_map_data_fdt *daf;
253 struct bcm_intc_softc *sc;
256 if (data->type != INTR_MAP_DATA_FDT)
259 daf = (struct intr_map_data_fdt *)data;
260 if (daf->ncells == 1)
262 else if (daf->ncells == 2) {
264 switch (daf->cells[0]) {
267 if (irq >= BANK1_START)
271 irq = daf->cells[1] + BANK1_START;
276 irq = daf->cells[1] + BANK2_START;
287 "invalid IRQ config: bank=%d, irq=%d\n",
288 daf->cells[0], daf->cells[1]);
295 if (irq >= BCM_INTC_NIRQS)
298 sc = device_get_softc(dev);
299 *isrcp = &sc->intc_isrcs[irq].bii_isrc;
304 bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
307 bcm_intc_disable_intr(dev, isrc);
311 bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
314 bcm_intc_enable_intr(dev, isrc);
318 bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc)
323 bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref)
325 struct bcm_intc_irqsrc *bii;
330 name = device_get_nameunit(sc->sc_dev);
331 for (irq = 0; irq < BCM_INTC_NIRQS; irq++) {
332 bii = &sc->intc_isrcs[irq];
334 if (IS_IRQ_BASIC(irq)) {
335 bii->bii_disable_reg = INTC_DISABLE_BASIC;
336 bii->bii_enable_reg = INTC_ENABLE_BASIC;
337 bii->bii_mask = 1 << irq;
338 } else if (IS_IRQ_BANK1(irq)) {
339 bii->bii_disable_reg = INTC_DISABLE_BANK1;
340 bii->bii_enable_reg = INTC_ENABLE_BANK1;
341 bii->bii_mask = 1 << IRQ_BANK1(irq);
342 } else if (IS_IRQ_BANK2(irq)) {
343 bii->bii_disable_reg = INTC_DISABLE_BANK2;
344 bii->bii_enable_reg = INTC_ENABLE_BANK2;
345 bii->bii_mask = 1 << IRQ_BANK2(irq);
349 error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0,
354 if (intr_pic_register(sc->sc_dev, xref) == NULL)
361 bcm_intc_probe(device_t dev)
364 if (!ofw_bus_status_okay(dev))
367 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic") &&
368 !ofw_bus_is_compatible(dev, "brcm,bcm2836-armctrl-ic"))
370 device_set_desc(dev, "BCM2835 Interrupt Controller");
371 return (BUS_PROBE_DEFAULT);
375 bcm_intc_attach(device_t dev)
377 struct bcm_intc_softc *sc = device_get_softc(dev);
385 sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
386 if (sc->intc_res == NULL) {
387 device_printf(dev, "could not allocate memory resource\n");
391 xref = OF_xref_from_node(ofw_bus_get_node(dev));
392 if (bcm_intc_pic_register(sc, xref) != 0) {
393 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res);
394 device_printf(dev, "could not register PIC\n");
399 sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
401 if (sc->intc_irq_res == NULL) {
402 if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) {
404 device_printf(dev, "could not set PIC as a root\n");
408 if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK,
409 bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) {
411 device_printf(dev, "could not setup irq handler\n");
415 sc->intc_bst = rman_get_bustag(sc->intc_res);
416 sc->intc_bsh = rman_get_bushandle(sc->intc_res);
423 static device_method_t bcm_intc_methods[] = {
424 DEVMETHOD(device_probe, bcm_intc_probe),
425 DEVMETHOD(device_attach, bcm_intc_attach),
427 DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr),
428 DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr),
429 DEVMETHOD(pic_map_intr, bcm_intc_map_intr),
430 DEVMETHOD(pic_post_filter, bcm_intc_post_filter),
431 DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread),
432 DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread),
437 static driver_t bcm_intc_driver = {
440 sizeof(struct bcm_intc_softc),
443 static devclass_t bcm_intc_devclass;
445 EARLY_DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass,
446 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);