2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/sysctl.h>
42 #include <sys/taskqueue.h>
44 #include <machine/bus.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/mmc/bridge.h>
50 #include <dev/mmc/mmcreg.h>
52 #include <dev/sdhci/sdhci.h>
57 #include "opt_mmccam.h"
59 #include "bcm2835_dma.h"
60 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
61 #include "bcm2835_vcbus.h"
63 #define BCM2835_DEFAULT_SDHCI_FREQ 50
65 #define BCM_SDHCI_BUFFER_SIZE 512
66 #define NUM_DMA_SEGS 2
69 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
70 printf(fmt,##args); } while (0)
72 #define dprintf(fmt, args...)
75 static int bcm2835_sdhci_hs = 1;
76 static int bcm2835_sdhci_pio_mode = 0;
78 static struct ofw_compat_data compat_data[] = {
79 {"broadcom,bcm2835-sdhci", 1},
80 {"brcm,bcm2835-sdhci", 1},
81 {"brcm,bcm2835-mmc", 1},
85 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
86 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
88 struct bcm_sdhci_softc {
90 struct resource * sc_mem_res;
91 struct resource * sc_irq_res;
92 bus_space_tag_t sc_bst;
93 bus_space_handle_t sc_bsh;
95 struct mmc_request * sc_req;
96 struct sdhci_slot sc_slot;
98 bus_dma_tag_t sc_dma_tag;
99 bus_dmamap_t sc_dma_map;
100 vm_paddr_t sc_sdhci_buffer_phys;
101 uint32_t cmd_and_mode;
102 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
103 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
104 int dmamap_seg_count;
105 int dmamap_seg_index;
109 static int bcm_sdhci_probe(device_t);
110 static int bcm_sdhci_attach(device_t);
111 static int bcm_sdhci_detach(device_t);
112 static void bcm_sdhci_intr(void *);
114 static int bcm_sdhci_get_ro(device_t, device_t);
115 static void bcm_sdhci_dma_intr(int ch, void *arg);
118 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
120 struct bcm_sdhci_softc *sc = arg;
123 sc->dmamap_status = err;
124 sc->dmamap_seg_count = nseg;
126 /* Note nseg is guaranteed to be zero if err is non-zero. */
127 for (i = 0; i < nseg; i++) {
128 sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
129 sc->dmamap_seg_sizes[i] = segs[i].ds_len;
134 bcm_sdhci_probe(device_t dev)
137 if (!ofw_bus_status_okay(dev))
140 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
143 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
145 return (BUS_PROBE_DEFAULT);
149 bcm_sdhci_attach(device_t dev)
151 struct bcm_sdhci_softc *sc = device_get_softc(dev);
160 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC,
164 device_printf(dev, "Unable to enable the power\n");
169 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC,
173 default_freq /= 1000000;
175 if (default_freq == 0) {
176 node = ofw_bus_get_node(sc->sc_dev);
177 if ((OF_getencprop(node, "clock-frequency", &cell,
179 default_freq = cell / 1000000;
181 if (default_freq == 0)
182 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
185 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
188 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
190 if (!sc->sc_mem_res) {
191 device_printf(dev, "cannot allocate memory window\n");
196 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
197 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
200 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
202 if (!sc->sc_irq_res) {
203 device_printf(dev, "cannot allocate interrupt\n");
208 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
209 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
210 device_printf(dev, "cannot setup interrupt handler\n");
215 if (!bcm2835_sdhci_pio_mode)
216 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
218 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
219 if (bcm2835_sdhci_hs)
220 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
221 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
222 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
223 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
224 | SDHCI_QUIRK_DONT_SET_HISPD_BIT
225 | SDHCI_QUIRK_MISSING_CAPS;
227 sdhci_init_slot(dev, &sc->sc_slot, 0);
229 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
230 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
233 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
235 /* Allocate bus_dma resources. */
236 err = bus_dma_tag_create(bus_get_dma_tag(dev),
237 1, 0, BUS_SPACE_MAXADDR_32BIT,
238 BUS_SPACE_MAXADDR, NULL, NULL,
239 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
240 BUS_DMA_ALLOCNOW, NULL, NULL,
244 device_printf(dev, "failed allocate DMA tag");
248 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
250 device_printf(dev, "bus_dmamap_create failed\n");
254 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */
255 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) +
258 bus_generic_probe(dev);
259 bus_generic_attach(dev);
261 sdhci_start_slot(&sc->sc_slot);
267 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
269 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
271 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
277 bcm_sdhci_detach(device_t dev)
284 bcm_sdhci_intr(void *arg)
286 struct bcm_sdhci_softc *sc = arg;
288 sdhci_generic_intr(&sc->sc_slot);
292 bcm_sdhci_get_ro(device_t bus, device_t child)
298 static inline uint32_t
299 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
301 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
306 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
309 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
311 * The Arasan HC has a bug where it may lose the content of
312 * consecutive writes to registers that are within two SD-card
313 * clock cycles of each other (a clock domain crossing problem).
315 if (sc->sc_slot.clock > 0)
316 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
320 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
322 struct bcm_sdhci_softc *sc = device_get_softc(dev);
323 uint32_t val = RD4(sc, off & ~3);
325 return ((val >> (off & 3)*8) & 0xff);
329 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
331 struct bcm_sdhci_softc *sc = device_get_softc(dev);
332 uint32_t val = RD4(sc, off & ~3);
335 * Standard 32-bit handling of command and transfer mode.
337 if (off == SDHCI_TRANSFER_MODE) {
338 return (sc->cmd_and_mode >> 16);
339 } else if (off == SDHCI_COMMAND_FLAGS) {
340 return (sc->cmd_and_mode & 0x0000ffff);
342 return ((val >> (off & 3)*8) & 0xffff);
346 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
348 struct bcm_sdhci_softc *sc = device_get_softc(dev);
354 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
355 uint32_t *data, bus_size_t count)
357 struct bcm_sdhci_softc *sc = device_get_softc(dev);
359 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
363 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
365 struct bcm_sdhci_softc *sc = device_get_softc(dev);
366 uint32_t val32 = RD4(sc, off & ~3);
367 val32 &= ~(0xff << (off & 3)*8);
368 val32 |= (val << (off & 3)*8);
369 WR4(sc, off & ~3, val32);
373 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
375 struct bcm_sdhci_softc *sc = device_get_softc(dev);
377 if (off == SDHCI_COMMAND_FLAGS)
378 val32 = sc->cmd_and_mode;
380 val32 = RD4(sc, off & ~3);
381 val32 &= ~(0xffff << (off & 3)*8);
382 val32 |= (val << (off & 3)*8);
383 if (off == SDHCI_TRANSFER_MODE)
384 sc->cmd_and_mode = val32;
386 WR4(sc, off & ~3, val32);
387 if (off == SDHCI_COMMAND_FLAGS)
388 sc->cmd_and_mode = val32;
393 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
395 struct bcm_sdhci_softc *sc = device_get_softc(dev);
400 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
401 uint32_t *data, bus_size_t count)
403 struct bcm_sdhci_softc *sc = device_get_softc(dev);
405 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
409 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
411 struct sdhci_slot *slot;
412 vm_paddr_t pdst, psrc;
413 int err, idx, len, sync_op;
416 idx = sc->dmamap_seg_index++;
417 len = sc->dmamap_seg_sizes[idx];
420 if (slot->curcmd->data->flags & MMC_DATA_READ) {
421 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
422 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
423 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
425 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
426 psrc = sc->sc_sdhci_buffer_phys;
427 pdst = sc->dmamap_seg_addrs[idx];
428 sync_op = BUS_DMASYNC_PREREAD;
430 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
432 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
433 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
434 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
435 psrc = sc->dmamap_seg_addrs[idx];
436 pdst = sc->sc_sdhci_buffer_phys;
437 sync_op = BUS_DMASYNC_PREWRITE;
441 * When starting a new DMA operation do the busdma sync operation, and
442 * disable SDCHI data interrrupts because we'll be driven by DMA
443 * interrupts (or SDHCI error interrupts) until the IO is done.
446 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
447 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
448 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
449 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
454 * Start the DMA transfer. Only programming errors (like failing to
455 * allocate a channel) cause a non-zero return from bcm_dma_start().
457 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
458 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
462 bcm_sdhci_dma_intr(int ch, void *arg)
464 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
465 struct sdhci_slot *slot = &sc->sc_slot;
469 mtx_lock(&slot->mtx);
472 * If there are more segments for the current dma, start the next one.
473 * Otherwise unload the dma map and decide what to do next based on the
474 * status of the sdhci controller and whether there's more data left.
476 if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
477 bcm_sdhci_start_dma_seg(sc);
478 mtx_unlock(&slot->mtx);
482 if (slot->curcmd->data->flags & MMC_DATA_READ) {
483 sync_op = BUS_DMASYNC_POSTREAD;
484 mask = SDHCI_INT_DATA_AVAIL;
486 sync_op = BUS_DMASYNC_POSTWRITE;
487 mask = SDHCI_INT_SPACE_AVAIL;
489 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
490 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
492 sc->dmamap_seg_count = 0;
493 sc->dmamap_seg_index = 0;
495 left = min(BCM_SDHCI_BUFFER_SIZE,
496 slot->curcmd->data->len - slot->offset);
499 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
501 if (reg & SDHCI_INT_DATA_END) {
502 /* ACK for all outstanding interrupts */
503 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
506 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
507 | SDHCI_INT_DATA_END;
508 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
511 /* finish this data */
512 sdhci_finish_data(slot);
515 /* already available? */
518 /* ACK for DATA_AVAIL or SPACE_AVAIL */
519 bcm_sdhci_write_4(slot->bus, slot,
520 SDHCI_INT_STATUS, mask);
522 /* continue next DMA transfer */
523 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
524 (uint8_t *)slot->curcmd->data->data +
525 slot->offset, left, bcm_sdhci_dmacb, sc,
526 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
527 slot->curcmd->error = MMC_ERR_NO_MEMORY;
528 sdhci_finish_data(slot);
530 bcm_sdhci_start_dma_seg(sc);
533 /* wait for next data by INT */
536 slot->intmask |= SDHCI_INT_DATA_AVAIL |
537 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
538 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
543 mtx_unlock(&slot->mtx);
547 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
549 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
552 if (sc->dmamap_seg_count != 0) {
553 device_printf(sc->sc_dev, "DMA in use\n");
557 left = min(BCM_SDHCI_BUFFER_SIZE,
558 slot->curcmd->data->len - slot->offset);
560 KASSERT((left & 3) == 0,
561 ("%s: len = %zu, not word-aligned", __func__, left));
563 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
564 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
565 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
566 sc->dmamap_status != 0) {
567 slot->curcmd->error = MMC_ERR_NO_MEMORY;
572 bcm_sdhci_start_dma_seg(sc);
576 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
578 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
581 if (sc->dmamap_seg_count != 0) {
582 device_printf(sc->sc_dev, "DMA in use\n");
586 left = min(BCM_SDHCI_BUFFER_SIZE,
587 slot->curcmd->data->len - slot->offset);
589 KASSERT((left & 3) == 0,
590 ("%s: len = %zu, not word-aligned", __func__, left));
592 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
593 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
594 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
595 sc->dmamap_status != 0) {
596 slot->curcmd->error = MMC_ERR_NO_MEMORY;
601 bcm_sdhci_start_dma_seg(sc);
605 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
610 * Do not use DMA for transfers less than block size or with a length
611 * that is not a multiple of four.
613 left = min(BCM_DMA_BLOCK_SIZE,
614 slot->curcmd->data->len - slot->offset);
615 if (left < BCM_DMA_BLOCK_SIZE)
624 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
628 /* DMA transfer FIFO 1KB */
629 if (slot->curcmd->data->flags & MMC_DATA_READ)
630 bcm_sdhci_read_dma(dev, slot);
632 bcm_sdhci_write_dma(dev, slot);
636 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
639 sdhci_finish_data(slot);
642 static device_method_t bcm_sdhci_methods[] = {
643 /* Device interface */
644 DEVMETHOD(device_probe, bcm_sdhci_probe),
645 DEVMETHOD(device_attach, bcm_sdhci_attach),
646 DEVMETHOD(device_detach, bcm_sdhci_detach),
649 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
650 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
652 /* MMC bridge interface */
653 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
654 DEVMETHOD(mmcbr_request, sdhci_generic_request),
655 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
656 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
657 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
659 /* Platform transfer methods */
660 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
661 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
662 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
663 /* SDHCI registers accessors */
664 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
665 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
666 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
667 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
668 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
669 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
670 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
671 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
676 static devclass_t bcm_sdhci_devclass;
678 static driver_t bcm_sdhci_driver = {
681 sizeof(struct bcm_sdhci_softc),
684 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass,
686 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);
688 MMC_DECLARE_BRIDGE(sdhci_bcm);