2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/sysctl.h>
42 #include <sys/taskqueue.h>
44 #include <machine/bus.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/mmc/bridge.h>
50 #include <dev/mmc/mmcreg.h>
52 #include <dev/sdhci/sdhci.h>
57 #include "opt_mmccam.h"
59 #include "bcm2835_dma.h"
60 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
61 #include "bcm2835_vcbus.h"
63 #define BCM2835_DEFAULT_SDHCI_FREQ 50
65 #define BCM_SDHCI_BUFFER_SIZE 512
66 #define NUM_DMA_SEGS 2
69 static int bcm2835_sdhci_debug = 0;
71 TUNABLE_INT("hw.bcm2835.sdhci.debug", &bcm2835_sdhci_debug);
72 SYSCTL_INT(_hw_sdhci, OID_AUTO, bcm2835_sdhci_debug, CTLFLAG_RWTUN,
73 &bcm2835_sdhci_debug, 0, "bcm2835 SDHCI debug level");
75 #define dprintf(fmt, args...) \
77 if (bcm2835_sdhci_debug) \
78 printf("%s: " fmt, __func__, ##args); \
81 #define dprintf(fmt, args...)
84 static int bcm2835_sdhci_hs = 1;
85 static int bcm2835_sdhci_pio_mode = 0;
87 static struct ofw_compat_data compat_data[] = {
88 {"broadcom,bcm2835-sdhci", 1},
89 {"brcm,bcm2835-sdhci", 1},
90 {"brcm,bcm2835-mmc", 1},
94 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
95 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
97 struct bcm_sdhci_softc {
99 struct resource * sc_mem_res;
100 struct resource * sc_irq_res;
101 bus_space_tag_t sc_bst;
102 bus_space_handle_t sc_bsh;
104 struct mmc_request * sc_req;
105 struct sdhci_slot sc_slot;
107 bus_dma_tag_t sc_dma_tag;
108 bus_dmamap_t sc_dma_map;
109 vm_paddr_t sc_sdhci_buffer_phys;
110 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
111 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
112 int dmamap_seg_count;
113 int dmamap_seg_index;
115 uint32_t blksz_and_count;
116 uint32_t cmd_and_mode;
117 bool need_update_blk;
120 static int bcm_sdhci_probe(device_t);
121 static int bcm_sdhci_attach(device_t);
122 static int bcm_sdhci_detach(device_t);
123 static void bcm_sdhci_intr(void *);
125 static int bcm_sdhci_get_ro(device_t, device_t);
126 static void bcm_sdhci_dma_intr(int ch, void *arg);
129 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
131 struct bcm_sdhci_softc *sc = arg;
134 sc->dmamap_status = err;
135 sc->dmamap_seg_count = nseg;
137 /* Note nseg is guaranteed to be zero if err is non-zero. */
138 for (i = 0; i < nseg; i++) {
139 sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
140 sc->dmamap_seg_sizes[i] = segs[i].ds_len;
145 bcm_sdhci_probe(device_t dev)
148 if (!ofw_bus_status_okay(dev))
151 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
154 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
156 return (BUS_PROBE_DEFAULT);
160 bcm_sdhci_attach(device_t dev)
162 struct bcm_sdhci_softc *sc = device_get_softc(dev);
171 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC,
175 device_printf(dev, "Unable to enable the power\n");
180 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC,
184 default_freq /= 1000000;
186 if (default_freq == 0) {
187 node = ofw_bus_get_node(sc->sc_dev);
188 if ((OF_getencprop(node, "clock-frequency", &cell,
190 default_freq = cell / 1000000;
192 if (default_freq == 0)
193 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
196 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
199 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
201 if (!sc->sc_mem_res) {
202 device_printf(dev, "cannot allocate memory window\n");
207 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
208 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
211 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
213 if (!sc->sc_irq_res) {
214 device_printf(dev, "cannot allocate interrupt\n");
219 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
220 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
221 device_printf(dev, "cannot setup interrupt handler\n");
226 if (!bcm2835_sdhci_pio_mode)
227 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
229 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
230 if (bcm2835_sdhci_hs)
231 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
232 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
233 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
234 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
235 | SDHCI_QUIRK_DONT_SET_HISPD_BIT
236 | SDHCI_QUIRK_MISSING_CAPS;
238 sdhci_init_slot(dev, &sc->sc_slot, 0);
240 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
241 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
244 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
246 /* Allocate bus_dma resources. */
247 err = bus_dma_tag_create(bus_get_dma_tag(dev),
248 1, 0, BUS_SPACE_MAXADDR_32BIT,
249 BUS_SPACE_MAXADDR, NULL, NULL,
250 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
251 BUS_DMA_ALLOCNOW, NULL, NULL,
255 device_printf(dev, "failed allocate DMA tag");
259 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
261 device_printf(dev, "bus_dmamap_create failed\n");
265 /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */
266 sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) +
269 bus_generic_probe(dev);
270 bus_generic_attach(dev);
272 sdhci_start_slot(&sc->sc_slot);
274 /* Seed our copies. */
275 sc->blksz_and_count = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_BLOCK_SIZE);
276 sc->cmd_and_mode = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_TRANSFER_MODE);
282 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
284 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
286 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
292 bcm_sdhci_detach(device_t dev)
299 bcm_sdhci_intr(void *arg)
301 struct bcm_sdhci_softc *sc = arg;
303 sdhci_generic_intr(&sc->sc_slot);
307 bcm_sdhci_get_ro(device_t bus, device_t child)
313 static inline uint32_t
314 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
316 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
321 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
324 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
326 * The Arasan HC has a bug where it may lose the content of
327 * consecutive writes to registers that are within two SD-card
328 * clock cycles of each other (a clock domain crossing problem).
330 if (sc->sc_slot.clock > 0)
331 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
335 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
337 struct bcm_sdhci_softc *sc = device_get_softc(dev);
338 uint32_t val = RD4(sc, off & ~3);
340 return ((val >> (off & 3)*8) & 0xff);
344 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
346 struct bcm_sdhci_softc *sc = device_get_softc(dev);
350 * Standard 32-bit handling of command and transfer mode, as
351 * well as block size and count.
353 if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) &&
355 val32 = sc->blksz_and_count;
356 else if (off == SDHCI_TRANSFER_MODE || off == SDHCI_COMMAND_FLAGS)
357 val32 = sc->cmd_and_mode;
359 val32 = RD4(sc, off & ~3);
361 return ((val32 >> (off & 3)*8) & 0xffff);
365 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
367 struct bcm_sdhci_softc *sc = device_get_softc(dev);
373 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
374 uint32_t *data, bus_size_t count)
376 struct bcm_sdhci_softc *sc = device_get_softc(dev);
378 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
382 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
384 struct bcm_sdhci_softc *sc = device_get_softc(dev);
385 uint32_t val32 = RD4(sc, off & ~3);
386 val32 &= ~(0xff << (off & 3)*8);
387 val32 |= (val << (off & 3)*8);
388 WR4(sc, off & ~3, val32);
392 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
394 struct bcm_sdhci_softc *sc = device_get_softc(dev);
398 * If we have a queued up 16bit value for blk size or count, use and
399 * update the saved value rather than doing any real register access.
400 * If we did not touch either since the last write, then read from
401 * register as at least block count can change.
402 * Similarly, if we are about to issue a command, always use the saved
403 * value for transfer mode as we can never write that without issuing
406 if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) &&
408 val32 = sc->blksz_and_count;
409 else if (off == SDHCI_COMMAND_FLAGS)
410 val32 = sc->cmd_and_mode;
412 val32 = RD4(sc, off & ~3);
414 val32 &= ~(0xffff << (off & 3)*8);
415 val32 |= (val << (off & 3)*8);
417 if (off == SDHCI_TRANSFER_MODE)
418 sc->cmd_and_mode = val32;
419 else if (off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) {
420 sc->blksz_and_count = val32;
421 sc->need_update_blk = true;
423 if (off == SDHCI_COMMAND_FLAGS) {
424 /* If we saved blk writes, do them now before cmd. */
425 if (sc->need_update_blk) {
426 WR4(sc, SDHCI_BLOCK_SIZE, sc->blksz_and_count);
427 sc->need_update_blk = false;
429 /* Always save cmd and mode registers. */
430 sc->cmd_and_mode = val32;
432 WR4(sc, off & ~3, val32);
437 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
439 struct bcm_sdhci_softc *sc = device_get_softc(dev);
444 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
445 uint32_t *data, bus_size_t count)
447 struct bcm_sdhci_softc *sc = device_get_softc(dev);
449 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
453 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
455 struct sdhci_slot *slot;
456 vm_paddr_t pdst, psrc;
457 int err, idx, len, sync_op;
460 idx = sc->dmamap_seg_index++;
461 len = sc->dmamap_seg_sizes[idx];
464 if (slot->curcmd->data->flags & MMC_DATA_READ) {
465 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
466 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
467 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
469 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
470 psrc = sc->sc_sdhci_buffer_phys;
471 pdst = sc->dmamap_seg_addrs[idx];
472 sync_op = BUS_DMASYNC_PREREAD;
474 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
476 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
477 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
478 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
479 psrc = sc->dmamap_seg_addrs[idx];
480 pdst = sc->sc_sdhci_buffer_phys;
481 sync_op = BUS_DMASYNC_PREWRITE;
485 * When starting a new DMA operation do the busdma sync operation, and
486 * disable SDCHI data interrrupts because we'll be driven by DMA
487 * interrupts (or SDHCI error interrupts) until the IO is done.
490 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
491 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
492 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
493 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
498 * Start the DMA transfer. Only programming errors (like failing to
499 * allocate a channel) cause a non-zero return from bcm_dma_start().
501 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
502 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
506 bcm_sdhci_dma_intr(int ch, void *arg)
508 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
509 struct sdhci_slot *slot = &sc->sc_slot;
513 mtx_lock(&slot->mtx);
516 * If there are more segments for the current dma, start the next one.
517 * Otherwise unload the dma map and decide what to do next based on the
518 * status of the sdhci controller and whether there's more data left.
520 if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
521 bcm_sdhci_start_dma_seg(sc);
522 mtx_unlock(&slot->mtx);
526 if (slot->curcmd->data->flags & MMC_DATA_READ) {
527 sync_op = BUS_DMASYNC_POSTREAD;
528 mask = SDHCI_INT_DATA_AVAIL;
530 sync_op = BUS_DMASYNC_POSTWRITE;
531 mask = SDHCI_INT_SPACE_AVAIL;
533 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
534 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
536 sc->dmamap_seg_count = 0;
537 sc->dmamap_seg_index = 0;
539 left = min(BCM_SDHCI_BUFFER_SIZE,
540 slot->curcmd->data->len - slot->offset);
543 * If there is less than buffer size outstanding, we would not handle
544 * it anymore using DMA if bcm_sdhci_will_handle_transfer() were asked.
545 * Re-enable interrupts and return and let the SDHCI state machine
548 if (left < BCM_SDHCI_BUFFER_SIZE) {
549 /* Re-enable data interrupts. */
550 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
552 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
554 mtx_unlock(&slot->mtx);
559 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
561 if (reg & SDHCI_INT_DATA_END) {
562 /* ACK for all outstanding interrupts */
563 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
566 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
567 | SDHCI_INT_DATA_END;
568 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
571 /* finish this data */
572 sdhci_finish_data(slot);
575 /* already available? */
578 /* ACK for DATA_AVAIL or SPACE_AVAIL */
579 bcm_sdhci_write_4(slot->bus, slot,
580 SDHCI_INT_STATUS, mask);
582 /* continue next DMA transfer */
583 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
584 (uint8_t *)slot->curcmd->data->data +
585 slot->offset, left, bcm_sdhci_dmacb, sc,
586 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
587 slot->curcmd->error = MMC_ERR_NO_MEMORY;
588 sdhci_finish_data(slot);
590 bcm_sdhci_start_dma_seg(sc);
593 /* wait for next data by INT */
596 slot->intmask |= SDHCI_INT_DATA_AVAIL |
597 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
598 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
603 mtx_unlock(&slot->mtx);
607 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
609 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
612 if (sc->dmamap_seg_count != 0) {
613 device_printf(sc->sc_dev, "DMA in use\n");
617 left = min(BCM_SDHCI_BUFFER_SIZE,
618 slot->curcmd->data->len - slot->offset);
620 KASSERT((left & 3) == 0,
621 ("%s: len = %zu, not word-aligned", __func__, left));
623 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
624 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
625 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
626 sc->dmamap_status != 0) {
627 slot->curcmd->error = MMC_ERR_NO_MEMORY;
632 bcm_sdhci_start_dma_seg(sc);
636 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
638 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
641 if (sc->dmamap_seg_count != 0) {
642 device_printf(sc->sc_dev, "DMA in use\n");
646 left = min(BCM_SDHCI_BUFFER_SIZE,
647 slot->curcmd->data->len - slot->offset);
649 KASSERT((left & 3) == 0,
650 ("%s: len = %zu, not word-aligned", __func__, left));
652 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
653 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
654 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
655 sc->dmamap_status != 0) {
656 slot->curcmd->error = MMC_ERR_NO_MEMORY;
661 bcm_sdhci_start_dma_seg(sc);
665 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
670 * Do not use DMA for transfers less than block size or with a length
671 * that is not a multiple of four.
673 left = min(BCM_DMA_BLOCK_SIZE,
674 slot->curcmd->data->len - slot->offset);
675 if (left < BCM_DMA_BLOCK_SIZE)
684 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
688 /* DMA transfer FIFO 1KB */
689 if (slot->curcmd->data->flags & MMC_DATA_READ)
690 bcm_sdhci_read_dma(dev, slot);
692 bcm_sdhci_write_dma(dev, slot);
696 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
699 sdhci_finish_data(slot);
702 static device_method_t bcm_sdhci_methods[] = {
703 /* Device interface */
704 DEVMETHOD(device_probe, bcm_sdhci_probe),
705 DEVMETHOD(device_attach, bcm_sdhci_attach),
706 DEVMETHOD(device_detach, bcm_sdhci_detach),
709 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
710 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
711 DEVMETHOD(bus_add_child, bus_generic_add_child),
713 /* MMC bridge interface */
714 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
715 DEVMETHOD(mmcbr_request, sdhci_generic_request),
716 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
717 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
718 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
720 /* Platform transfer methods */
721 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
722 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
723 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
724 /* SDHCI registers accessors */
725 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
726 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
727 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
728 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
729 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
730 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
731 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
732 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
737 static devclass_t bcm_sdhci_devclass;
739 static driver_t bcm_sdhci_driver = {
742 sizeof(struct bcm_sdhci_softc),
745 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass,
747 SDHCI_DEPEND(sdhci_bcm);
749 MMC_DECLARE_BRIDGE(sdhci_bcm);