2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/kthread.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/queue.h>
43 #include <sys/resource.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
48 #include <sys/timetc.h>
49 #include <sys/watchdog.h>
53 #include <machine/bus.h>
54 #include <machine/cpu.h>
55 #include <machine/cpufunc.h>
56 #include <machine/resource.h>
57 #include <machine/intr.h>
59 #include <dev/fdt/fdt_common.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/mmc/bridge.h>
64 #include <dev/mmc/mmcreg.h>
65 #include <dev/mmc/mmcbrvar.h>
67 #include <dev/sdhci/sdhci.h>
70 #include "bcm2835_dma.h"
71 #include "bcm2835_vcbus.h"
73 #define BCM2835_DEFAULT_SDHCI_FREQ 50
75 #define BCM_SDHCI_BUFFER_SIZE 512
78 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
79 printf(fmt,##args); } while (0)
81 #define dprintf(fmt, args...)
85 * Arasan HC seems to have problem with Data CRC on lower frequencies.
86 * Use this tunable to cap initialization sequence frequency at higher
87 * value. Default is standard 400kHz
89 static int bcm2835_sdhci_min_freq = 400000;
90 static int bcm2835_sdhci_hs = 1;
91 static int bcm2835_sdhci_pio_mode = 0;
93 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
94 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
95 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
97 struct bcm_sdhci_dmamap_arg {
98 bus_addr_t sc_dma_busaddr;
101 struct bcm_sdhci_softc {
104 struct resource * sc_mem_res;
105 struct resource * sc_irq_res;
106 bus_space_tag_t sc_bst;
107 bus_space_handle_t sc_bsh;
109 struct mmc_request * sc_req;
110 struct mmc_data * sc_data;
112 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
113 int sc_xfer_direction;
114 #define DIRECTION_READ 0
115 #define DIRECTION_WRITE 1
118 struct sdhci_slot sc_slot;
121 bus_dma_tag_t sc_dma_tag;
122 bus_dmamap_t sc_dma_map;
123 vm_paddr_t sc_sdhci_buffer_phys;
126 static int bcm_sdhci_probe(device_t);
127 static int bcm_sdhci_attach(device_t);
128 static int bcm_sdhci_detach(device_t);
129 static void bcm_sdhci_intr(void *);
131 static int bcm_sdhci_get_ro(device_t, device_t);
132 static void bcm_sdhci_dma_intr(int ch, void *arg);
134 #define bcm_sdhci_lock(_sc) \
135 mtx_lock(&_sc->sc_mtx);
136 #define bcm_sdhci_unlock(_sc) \
137 mtx_unlock(&_sc->sc_mtx);
140 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
148 addr = (bus_addr_t*)arg;
149 *addr = segs[0].ds_addr;
153 bcm_sdhci_probe(device_t dev)
156 if (!ofw_bus_status_okay(dev))
159 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
162 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
163 return (BUS_PROBE_DEFAULT);
167 bcm_sdhci_attach(device_t dev)
169 struct bcm_sdhci_softc *sc = device_get_softc(dev);
179 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
180 node = ofw_bus_get_node(sc->sc_dev);
181 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
182 default_freq = (int)fdt32_to_cpu(cell)/1000000;
184 dprintf("SDHCI frequency: %dMHz\n", default_freq);
186 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
189 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
191 if (!sc->sc_mem_res) {
192 device_printf(dev, "cannot allocate memory window\n");
197 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
198 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
201 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
203 if (!sc->sc_irq_res) {
204 device_printf(dev, "cannot allocate interrupt\n");
205 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
210 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
211 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand))
213 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
214 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
215 device_printf(dev, "cannot setup interrupt handler\n");
220 if (!bcm2835_sdhci_pio_mode)
221 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
223 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
224 if (bcm2835_sdhci_hs)
225 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
226 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
227 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
228 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
229 | SDHCI_QUIRK_MISSING_CAPS;
231 sdhci_init_slot(dev, &sc->sc_slot, 0);
233 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
234 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
235 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
236 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
237 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
238 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
241 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
243 /* Allocate bus_dma resources. */
244 err = bus_dma_tag_create(bus_get_dma_tag(dev),
245 1, 0, BUS_SPACE_MAXADDR_32BIT,
246 BUS_SPACE_MAXADDR, NULL, NULL,
247 BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE,
248 BUS_DMA_ALLOCNOW, NULL, NULL,
252 device_printf(dev, "failed allocate DMA tag");
256 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
258 device_printf(dev, "bus_dmamap_create failed\n");
262 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
265 bus_generic_probe(dev);
266 bus_generic_attach(dev);
268 sdhci_start_slot(&sc->sc_slot);
274 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
276 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
278 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
284 bcm_sdhci_detach(device_t dev)
291 bcm_sdhci_intr(void *arg)
293 struct bcm_sdhci_softc *sc = arg;
295 sdhci_generic_intr(&sc->sc_slot);
299 bcm_sdhci_get_ro(device_t bus, device_t child)
305 static inline uint32_t
306 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
308 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
313 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
315 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
317 if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL))
319 int timeout = 100000;
320 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)
325 printf("sdhci_brcm: writing 0x%X to reg 0x%X "
326 "always gives 0x%X\n",
328 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off));
333 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
335 struct bcm_sdhci_softc *sc = device_get_softc(dev);
336 uint32_t val = RD4(sc, off & ~3);
338 return ((val >> (off & 3)*8) & 0xff);
342 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
344 struct bcm_sdhci_softc *sc = device_get_softc(dev);
345 uint32_t val = RD4(sc, off & ~3);
347 return ((val >> (off & 3)*8) & 0xffff);
351 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
353 struct bcm_sdhci_softc *sc = device_get_softc(dev);
359 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
360 uint32_t *data, bus_size_t count)
362 struct bcm_sdhci_softc *sc = device_get_softc(dev);
364 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
368 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
370 struct bcm_sdhci_softc *sc = device_get_softc(dev);
371 uint32_t val32 = RD4(sc, off & ~3);
372 val32 &= ~(0xff << (off & 3)*8);
373 val32 |= (val << (off & 3)*8);
374 WR4(sc, off & ~3, val32);
378 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
380 struct bcm_sdhci_softc *sc = device_get_softc(dev);
381 static uint32_t cmd_and_trandfer_mode;
383 if (off == SDHCI_COMMAND_FLAGS)
384 val32 = cmd_and_trandfer_mode;
386 val32 = RD4(sc, off & ~3);
387 val32 &= ~(0xffff << (off & 3)*8);
388 val32 |= (val << (off & 3)*8);
389 if (off == SDHCI_TRANSFER_MODE)
390 cmd_and_trandfer_mode = val32;
392 WR4(sc, off & ~3, val32);
396 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
398 struct bcm_sdhci_softc *sc = device_get_softc(dev);
403 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
404 uint32_t *data, bus_size_t count)
406 struct bcm_sdhci_softc *sc = device_get_softc(dev);
408 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
412 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
415 return bcm2835_sdhci_min_freq;
419 bcm_sdhci_dma_intr(int ch, void *arg)
421 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
422 struct sdhci_slot *slot = &sc->sc_slot;
425 vm_paddr_t pdst, psrc;
429 mtx_lock(&slot->mtx);
431 len = bcm_dma_length(sc->sc_dma_ch);
432 if (slot->curcmd->data->flags & MMC_DATA_READ) {
433 sync_op = BUS_DMASYNC_POSTREAD;
434 mask = SDHCI_INT_DATA_AVAIL;
436 sync_op = BUS_DMASYNC_POSTWRITE;
437 mask = SDHCI_INT_SPACE_AVAIL;
439 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
440 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
443 sc->sc_dma_inuse = 0;
445 left = min(BCM_SDHCI_BUFFER_SIZE,
446 slot->curcmd->data->len - slot->offset);
449 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
451 if (reg & SDHCI_INT_DATA_END) {
452 /* ACK for all outstanding interrupts */
453 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
456 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
457 | SDHCI_INT_DATA_END;
458 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
461 /* finish this data */
462 sdhci_finish_data(slot);
465 /* already available? */
467 sc->sc_dma_inuse = 1;
469 /* ACK for DATA_AVAIL or SPACE_AVAIL */
470 bcm_sdhci_write_4(slot->bus, slot,
471 SDHCI_INT_STATUS, mask);
473 /* continue next DMA transfer */
474 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
475 (uint8_t *)slot->curcmd->data->data +
476 slot->offset, left, bcm_dmamap_cb, &pmem, 0);
477 if (slot->curcmd->data->flags & MMC_DATA_READ) {
478 psrc = sc->sc_sdhci_buffer_phys;
480 sync_op = BUS_DMASYNC_PREREAD;
483 pdst = sc->sc_sdhci_buffer_phys;
484 sync_op = BUS_DMASYNC_PREWRITE;
486 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
487 if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) {
488 /* XXX stop xfer, other error recovery? */
489 device_printf(sc->sc_dev, "failed DMA start\n");
492 /* wait for next data by INT */
495 slot->intmask |= SDHCI_INT_DATA_AVAIL |
496 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
497 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
502 mtx_unlock(&slot->mtx);
506 bcm_sdhci_read_dma(struct sdhci_slot *slot)
508 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
512 if (sc->sc_dma_inuse) {
513 device_printf(sc->sc_dev, "DMA in use\n");
517 sc->sc_dma_inuse = 1;
519 left = min(BCM_SDHCI_BUFFER_SIZE,
520 slot->curcmd->data->len - slot->offset);
522 KASSERT((left & 3) == 0,
523 ("%s: len = %d, not word-aligned", __func__, left));
525 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
526 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
527 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
529 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
531 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
532 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
533 bcm_dmamap_cb, &paddr, 0);
535 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
536 BUS_DMASYNC_PREREAD);
539 if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys,
541 device_printf(sc->sc_dev, "failed DMA start\n");
545 bcm_sdhci_write_dma(struct sdhci_slot *slot)
547 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
551 if (sc->sc_dma_inuse) {
552 device_printf(sc->sc_dev, "DMA in use\n");
556 sc->sc_dma_inuse = 1;
558 left = min(BCM_SDHCI_BUFFER_SIZE,
559 slot->curcmd->data->len - slot->offset);
561 KASSERT((left & 3) == 0,
562 ("%s: len = %d, not word-aligned", __func__, left));
564 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
565 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
566 bcm_dmamap_cb, &paddr, 0);
568 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
570 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
571 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
572 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
574 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
575 BUS_DMASYNC_PREWRITE);
578 if (bcm_dma_start(sc->sc_dma_ch, paddr,
579 sc->sc_sdhci_buffer_phys, left) != 0)
580 device_printf(sc->sc_dev, "failed DMA start\n");
584 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
589 * Do not use DMA for transfers less than block size or with a length
590 * that is not a multiple of four.
592 left = min(BCM_DMA_BLOCK_SIZE,
593 slot->curcmd->data->len - slot->offset);
594 if (left < BCM_DMA_BLOCK_SIZE)
603 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
608 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
609 bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
611 /* DMA transfer FIFO 1KB */
612 if (slot->curcmd->data->flags & MMC_DATA_READ)
613 bcm_sdhci_read_dma(slot);
615 bcm_sdhci_write_dma(slot);
619 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
622 sdhci_finish_data(slot);
625 static device_method_t bcm_sdhci_methods[] = {
626 /* Device interface */
627 DEVMETHOD(device_probe, bcm_sdhci_probe),
628 DEVMETHOD(device_attach, bcm_sdhci_attach),
629 DEVMETHOD(device_detach, bcm_sdhci_detach),
632 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
633 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
634 DEVMETHOD(bus_print_child, bus_generic_print_child),
636 /* MMC bridge interface */
637 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
638 DEVMETHOD(mmcbr_request, sdhci_generic_request),
639 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
640 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
641 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
643 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq),
644 /* Platform transfer methods */
645 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
646 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
647 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
648 /* SDHCI registers accessors */
649 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
650 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
651 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
652 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
653 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
654 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
655 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
656 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
661 static devclass_t bcm_sdhci_devclass;
663 static driver_t bcm_sdhci_driver = {
666 sizeof(struct bcm_sdhci_softc),
669 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
670 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);