2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/kthread.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/queue.h>
43 #include <sys/resource.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
48 #include <sys/timetc.h>
49 #include <sys/watchdog.h>
53 #include <machine/bus.h>
54 #include <machine/cpu.h>
55 #include <machine/cpufunc.h>
56 #include <machine/resource.h>
57 #include <machine/intr.h>
59 #include <dev/fdt/fdt_common.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/mmc/bridge.h>
64 #include <dev/mmc/mmcreg.h>
65 #include <dev/mmc/mmcbrvar.h>
67 #include <dev/sdhci/sdhci.h>
70 #include "bcm2835_dma.h"
71 #include "bcm2835_vcbus.h"
73 #define BCM2835_DEFAULT_SDHCI_FREQ 50
75 #define BCM_SDHCI_BUFFER_SIZE 512
78 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
79 printf(fmt,##args); } while (0)
81 #define dprintf(fmt, args...)
85 * Arasan HC seems to have problem with Data CRC on lower frequencies.
86 * Use this tunable to cap initialization sequence frequency at higher
87 * value. Default is standard 400kHz.
88 * HS mode brings too many problems for most of cards, so disable HS mode
89 * until a better fix comes up.
90 * HS mode still can be enabled with the tunable.
92 static int bcm2835_sdhci_min_freq = 400000;
93 static int bcm2835_sdhci_hs = 0;
94 static int bcm2835_sdhci_pio_mode = 0;
96 TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
97 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
98 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
100 struct bcm_sdhci_dmamap_arg {
101 bus_addr_t sc_dma_busaddr;
104 struct bcm_sdhci_softc {
107 struct resource * sc_mem_res;
108 struct resource * sc_irq_res;
109 bus_space_tag_t sc_bst;
110 bus_space_handle_t sc_bsh;
112 struct mmc_request * sc_req;
113 struct mmc_data * sc_data;
115 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
116 int sc_xfer_direction;
117 #define DIRECTION_READ 0
118 #define DIRECTION_WRITE 1
121 struct sdhci_slot sc_slot;
124 bus_dma_tag_t sc_dma_tag;
125 bus_dmamap_t sc_dma_map;
126 vm_paddr_t sc_sdhci_buffer_phys;
129 static int bcm_sdhci_probe(device_t);
130 static int bcm_sdhci_attach(device_t);
131 static int bcm_sdhci_detach(device_t);
132 static void bcm_sdhci_intr(void *);
134 static int bcm_sdhci_get_ro(device_t, device_t);
135 static void bcm_sdhci_dma_intr(int ch, void *arg);
137 #define bcm_sdhci_lock(_sc) \
138 mtx_lock(&_sc->sc_mtx);
139 #define bcm_sdhci_unlock(_sc) \
140 mtx_unlock(&_sc->sc_mtx);
143 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
151 addr = (bus_addr_t*)arg;
152 *addr = segs[0].ds_addr;
156 bcm_sdhci_probe(device_t dev)
159 if (!ofw_bus_status_okay(dev))
162 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
165 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
166 return (BUS_PROBE_DEFAULT);
170 bcm_sdhci_attach(device_t dev)
172 struct bcm_sdhci_softc *sc = device_get_softc(dev);
182 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
183 node = ofw_bus_get_node(sc->sc_dev);
184 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
185 default_freq = (int)fdt32_to_cpu(cell)/1000000;
187 dprintf("SDHCI frequency: %dMHz\n", default_freq);
189 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
192 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
194 if (!sc->sc_mem_res) {
195 device_printf(dev, "cannot allocate memory window\n");
200 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
201 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
204 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
206 if (!sc->sc_irq_res) {
207 device_printf(dev, "cannot allocate interrupt\n");
208 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
213 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
214 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand))
216 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
217 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
218 device_printf(dev, "cannot setup interrupt handler\n");
223 if (!bcm2835_sdhci_pio_mode)
224 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
226 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
227 if (bcm2835_sdhci_hs)
228 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
229 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
230 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
231 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
232 | SDHCI_QUIRK_MISSING_CAPS;
234 sdhci_init_slot(dev, &sc->sc_slot, 0);
236 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
237 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
238 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
239 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
240 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
241 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
244 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
246 /* Allocate bus_dma resources. */
247 err = bus_dma_tag_create(bus_get_dma_tag(dev),
248 1, 0, BUS_SPACE_MAXADDR_32BIT,
249 BUS_SPACE_MAXADDR, NULL, NULL,
250 BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE,
251 BUS_DMA_ALLOCNOW, NULL, NULL,
255 device_printf(dev, "failed allocate DMA tag");
259 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
261 device_printf(dev, "bus_dmamap_create failed\n");
265 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
268 bus_generic_probe(dev);
269 bus_generic_attach(dev);
271 sdhci_start_slot(&sc->sc_slot);
277 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
279 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
281 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
287 bcm_sdhci_detach(device_t dev)
294 bcm_sdhci_intr(void *arg)
296 struct bcm_sdhci_softc *sc = arg;
298 sdhci_generic_intr(&sc->sc_slot);
302 bcm_sdhci_get_ro(device_t bus, device_t child)
308 static inline uint32_t
309 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
311 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
316 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
319 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
321 * The Arasan HC has a bug where it may lose the content of
322 * consecutive writes to registers that are within two SD-card
323 * clock cycles of each other (a clock domain crossing problem).
325 if (sc->sc_slot.clock > 0)
326 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
330 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
332 struct bcm_sdhci_softc *sc = device_get_softc(dev);
333 uint32_t val = RD4(sc, off & ~3);
335 return ((val >> (off & 3)*8) & 0xff);
339 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
341 struct bcm_sdhci_softc *sc = device_get_softc(dev);
342 uint32_t val = RD4(sc, off & ~3);
344 return ((val >> (off & 3)*8) & 0xffff);
348 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
350 struct bcm_sdhci_softc *sc = device_get_softc(dev);
356 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
357 uint32_t *data, bus_size_t count)
359 struct bcm_sdhci_softc *sc = device_get_softc(dev);
361 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
365 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
367 struct bcm_sdhci_softc *sc = device_get_softc(dev);
368 uint32_t val32 = RD4(sc, off & ~3);
369 val32 &= ~(0xff << (off & 3)*8);
370 val32 |= (val << (off & 3)*8);
371 WR4(sc, off & ~3, val32);
375 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
377 struct bcm_sdhci_softc *sc = device_get_softc(dev);
378 static uint32_t cmd_and_trandfer_mode;
380 if (off == SDHCI_COMMAND_FLAGS)
381 val32 = cmd_and_trandfer_mode;
383 val32 = RD4(sc, off & ~3);
384 val32 &= ~(0xffff << (off & 3)*8);
385 val32 |= (val << (off & 3)*8);
386 if (off == SDHCI_TRANSFER_MODE)
387 cmd_and_trandfer_mode = val32;
389 WR4(sc, off & ~3, val32);
393 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
395 struct bcm_sdhci_softc *sc = device_get_softc(dev);
400 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
401 uint32_t *data, bus_size_t count)
403 struct bcm_sdhci_softc *sc = device_get_softc(dev);
405 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
409 bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
412 return bcm2835_sdhci_min_freq;
416 bcm_sdhci_dma_intr(int ch, void *arg)
418 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
419 struct sdhci_slot *slot = &sc->sc_slot;
422 vm_paddr_t pdst, psrc;
426 mtx_lock(&slot->mtx);
428 len = bcm_dma_length(sc->sc_dma_ch);
429 if (slot->curcmd->data->flags & MMC_DATA_READ) {
430 sync_op = BUS_DMASYNC_POSTREAD;
431 mask = SDHCI_INT_DATA_AVAIL;
433 sync_op = BUS_DMASYNC_POSTWRITE;
434 mask = SDHCI_INT_SPACE_AVAIL;
436 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
437 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
440 sc->sc_dma_inuse = 0;
442 left = min(BCM_SDHCI_BUFFER_SIZE,
443 slot->curcmd->data->len - slot->offset);
446 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
448 if (reg & SDHCI_INT_DATA_END) {
449 /* ACK for all outstanding interrupts */
450 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
453 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
454 | SDHCI_INT_DATA_END;
455 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
458 /* finish this data */
459 sdhci_finish_data(slot);
462 /* already available? */
464 sc->sc_dma_inuse = 1;
466 /* ACK for DATA_AVAIL or SPACE_AVAIL */
467 bcm_sdhci_write_4(slot->bus, slot,
468 SDHCI_INT_STATUS, mask);
470 /* continue next DMA transfer */
471 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
472 (uint8_t *)slot->curcmd->data->data +
473 slot->offset, left, bcm_dmamap_cb, &pmem, 0);
474 if (slot->curcmd->data->flags & MMC_DATA_READ) {
475 psrc = sc->sc_sdhci_buffer_phys;
477 sync_op = BUS_DMASYNC_PREREAD;
480 pdst = sc->sc_sdhci_buffer_phys;
481 sync_op = BUS_DMASYNC_PREWRITE;
483 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
484 if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) {
485 /* XXX stop xfer, other error recovery? */
486 device_printf(sc->sc_dev, "failed DMA start\n");
489 /* wait for next data by INT */
492 slot->intmask |= SDHCI_INT_DATA_AVAIL |
493 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
494 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
499 mtx_unlock(&slot->mtx);
503 bcm_sdhci_read_dma(struct sdhci_slot *slot)
505 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
509 if (sc->sc_dma_inuse) {
510 device_printf(sc->sc_dev, "DMA in use\n");
514 sc->sc_dma_inuse = 1;
516 left = min(BCM_SDHCI_BUFFER_SIZE,
517 slot->curcmd->data->len - slot->offset);
519 KASSERT((left & 3) == 0,
520 ("%s: len = %d, not word-aligned", __func__, left));
522 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
523 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
524 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
526 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
528 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
529 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
530 bcm_dmamap_cb, &paddr, 0);
532 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
533 BUS_DMASYNC_PREREAD);
536 if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys,
538 device_printf(sc->sc_dev, "failed DMA start\n");
542 bcm_sdhci_write_dma(struct sdhci_slot *slot)
544 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
548 if (sc->sc_dma_inuse) {
549 device_printf(sc->sc_dev, "DMA in use\n");
553 sc->sc_dma_inuse = 1;
555 left = min(BCM_SDHCI_BUFFER_SIZE,
556 slot->curcmd->data->len - slot->offset);
558 KASSERT((left & 3) == 0,
559 ("%s: len = %d, not word-aligned", __func__, left));
561 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
562 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
563 bcm_dmamap_cb, &paddr, 0);
565 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
567 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
568 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
569 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
571 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
572 BUS_DMASYNC_PREWRITE);
575 if (bcm_dma_start(sc->sc_dma_ch, paddr,
576 sc->sc_sdhci_buffer_phys, left) != 0)
577 device_printf(sc->sc_dev, "failed DMA start\n");
581 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
586 * Do not use DMA for transfers less than block size or with a length
587 * that is not a multiple of four.
589 left = min(BCM_DMA_BLOCK_SIZE,
590 slot->curcmd->data->len - slot->offset);
591 if (left < BCM_DMA_BLOCK_SIZE)
600 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
605 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
606 bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
608 /* DMA transfer FIFO 1KB */
609 if (slot->curcmd->data->flags & MMC_DATA_READ)
610 bcm_sdhci_read_dma(slot);
612 bcm_sdhci_write_dma(slot);
616 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
619 sdhci_finish_data(slot);
622 static device_method_t bcm_sdhci_methods[] = {
623 /* Device interface */
624 DEVMETHOD(device_probe, bcm_sdhci_probe),
625 DEVMETHOD(device_attach, bcm_sdhci_attach),
626 DEVMETHOD(device_detach, bcm_sdhci_detach),
629 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
630 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
631 DEVMETHOD(bus_print_child, bus_generic_print_child),
633 /* MMC bridge interface */
634 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
635 DEVMETHOD(mmcbr_request, sdhci_generic_request),
636 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
637 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
638 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
640 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq),
641 /* Platform transfer methods */
642 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
643 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
644 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
645 /* SDHCI registers accessors */
646 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
647 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
648 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
649 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
650 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
651 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
652 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
653 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
658 static devclass_t bcm_sdhci_devclass;
660 static driver_t bcm_sdhci_driver = {
663 sizeof(struct bcm_sdhci_softc),
666 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
667 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);