2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/mmc/bridge.h>
49 #include <dev/mmc/mmcreg.h>
50 #include <dev/mmc/mmcbrvar.h>
52 #include <dev/sdhci/sdhci.h>
55 #include "bcm2835_dma.h"
56 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
57 #include "bcm2835_vcbus.h"
59 #define BCM2835_DEFAULT_SDHCI_FREQ 50
61 #define BCM_SDHCI_BUFFER_SIZE 512
62 #define NUM_DMA_SEGS 2
65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
66 printf(fmt,##args); } while (0)
68 #define dprintf(fmt, args...)
71 static int bcm2835_sdhci_hs = 1;
72 static int bcm2835_sdhci_pio_mode = 0;
74 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
75 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
77 struct bcm_sdhci_softc {
79 struct resource * sc_mem_res;
80 struct resource * sc_irq_res;
81 bus_space_tag_t sc_bst;
82 bus_space_handle_t sc_bsh;
84 struct mmc_request * sc_req;
85 struct sdhci_slot sc_slot;
87 bus_dma_tag_t sc_dma_tag;
88 bus_dmamap_t sc_dma_map;
89 vm_paddr_t sc_sdhci_buffer_phys;
90 uint32_t cmd_and_mode;
91 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
92 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
98 static int bcm_sdhci_probe(device_t);
99 static int bcm_sdhci_attach(device_t);
100 static int bcm_sdhci_detach(device_t);
101 static void bcm_sdhci_intr(void *);
103 static int bcm_sdhci_get_ro(device_t, device_t);
104 static void bcm_sdhci_dma_intr(int ch, void *arg);
107 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
109 struct bcm_sdhci_softc *sc = arg;
112 sc->dmamap_status = err;
113 sc->dmamap_seg_count = nseg;
115 /* Note nseg is guaranteed to be zero if err is non-zero. */
116 for (i = 0; i < nseg; i++) {
117 sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
118 sc->dmamap_seg_sizes[i] = segs[i].ds_len;
123 bcm_sdhci_probe(device_t dev)
126 if (!ofw_bus_status_okay(dev))
129 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
132 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
133 return (BUS_PROBE_DEFAULT);
137 bcm_sdhci_attach(device_t dev)
139 struct bcm_sdhci_softc *sc = device_get_softc(dev);
148 err = bcm2835_mbox_set_power_state(dev, BCM2835_MBOX_POWER_ID_EMMC,
152 device_printf(dev, "Unable to enable the power\n");
157 err = bcm2835_mbox_get_clock_rate(dev, BCM2835_MBOX_CLOCK_ID_EMMC,
161 default_freq /= 1000000;
163 if (default_freq == 0) {
164 node = ofw_bus_get_node(sc->sc_dev);
165 if ((OF_getencprop(node, "clock-frequency", &cell,
167 default_freq = cell / 1000000;
169 if (default_freq == 0)
170 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
173 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
176 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
178 if (!sc->sc_mem_res) {
179 device_printf(dev, "cannot allocate memory window\n");
184 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
185 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
188 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
190 if (!sc->sc_irq_res) {
191 device_printf(dev, "cannot allocate interrupt\n");
196 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
197 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
198 device_printf(dev, "cannot setup interrupt handler\n");
203 if (!bcm2835_sdhci_pio_mode)
204 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
206 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
207 if (bcm2835_sdhci_hs)
208 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
209 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
210 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
211 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
212 | SDHCI_QUIRK_DONT_SET_HISPD_BIT
213 | SDHCI_QUIRK_MISSING_CAPS;
215 sdhci_init_slot(dev, &sc->sc_slot, 0);
217 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
218 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
219 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
220 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
221 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
222 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
225 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
227 /* Allocate bus_dma resources. */
228 err = bus_dma_tag_create(bus_get_dma_tag(dev),
229 1, 0, BUS_SPACE_MAXADDR_32BIT,
230 BUS_SPACE_MAXADDR, NULL, NULL,
231 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
232 BUS_DMA_ALLOCNOW, NULL, NULL,
236 device_printf(dev, "failed allocate DMA tag");
240 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
242 device_printf(dev, "bus_dmamap_create failed\n");
246 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
249 bus_generic_probe(dev);
250 bus_generic_attach(dev);
252 sdhci_start_slot(&sc->sc_slot);
258 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
260 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
262 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
268 bcm_sdhci_detach(device_t dev)
275 bcm_sdhci_intr(void *arg)
277 struct bcm_sdhci_softc *sc = arg;
279 sdhci_generic_intr(&sc->sc_slot);
283 bcm_sdhci_get_ro(device_t bus, device_t child)
289 static inline uint32_t
290 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
292 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
297 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
300 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
302 * The Arasan HC has a bug where it may lose the content of
303 * consecutive writes to registers that are within two SD-card
304 * clock cycles of each other (a clock domain crossing problem).
306 if (sc->sc_slot.clock > 0)
307 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
311 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
313 struct bcm_sdhci_softc *sc = device_get_softc(dev);
314 uint32_t val = RD4(sc, off & ~3);
316 return ((val >> (off & 3)*8) & 0xff);
320 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
322 struct bcm_sdhci_softc *sc = device_get_softc(dev);
323 uint32_t val = RD4(sc, off & ~3);
326 * Standard 32-bit handling of command and transfer mode.
328 if (off == SDHCI_TRANSFER_MODE) {
329 return (sc->cmd_and_mode >> 16);
330 } else if (off == SDHCI_COMMAND_FLAGS) {
331 return (sc->cmd_and_mode & 0x0000ffff);
333 return ((val >> (off & 3)*8) & 0xffff);
337 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
339 struct bcm_sdhci_softc *sc = device_get_softc(dev);
345 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
346 uint32_t *data, bus_size_t count)
348 struct bcm_sdhci_softc *sc = device_get_softc(dev);
350 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
354 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
356 struct bcm_sdhci_softc *sc = device_get_softc(dev);
357 uint32_t val32 = RD4(sc, off & ~3);
358 val32 &= ~(0xff << (off & 3)*8);
359 val32 |= (val << (off & 3)*8);
360 WR4(sc, off & ~3, val32);
364 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
366 struct bcm_sdhci_softc *sc = device_get_softc(dev);
368 if (off == SDHCI_COMMAND_FLAGS)
369 val32 = sc->cmd_and_mode;
371 val32 = RD4(sc, off & ~3);
372 val32 &= ~(0xffff << (off & 3)*8);
373 val32 |= (val << (off & 3)*8);
374 if (off == SDHCI_TRANSFER_MODE)
375 sc->cmd_and_mode = val32;
377 WR4(sc, off & ~3, val32);
378 if (off == SDHCI_COMMAND_FLAGS)
379 sc->cmd_and_mode = val32;
384 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
386 struct bcm_sdhci_softc *sc = device_get_softc(dev);
391 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
392 uint32_t *data, bus_size_t count)
394 struct bcm_sdhci_softc *sc = device_get_softc(dev);
396 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
400 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
402 struct sdhci_slot *slot;
403 vm_paddr_t pdst, psrc;
404 int err, idx, len, sync_op;
407 idx = sc->dmamap_seg_index++;
408 len = sc->dmamap_seg_sizes[idx];
411 if (slot->curcmd->data->flags & MMC_DATA_READ) {
412 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
413 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
414 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
416 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
417 psrc = sc->sc_sdhci_buffer_phys;
418 pdst = sc->dmamap_seg_addrs[idx];
419 sync_op = BUS_DMASYNC_PREREAD;
421 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
423 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
424 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
425 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
426 psrc = sc->dmamap_seg_addrs[idx];
427 pdst = sc->sc_sdhci_buffer_phys;
428 sync_op = BUS_DMASYNC_PREWRITE;
432 * When starting a new DMA operation do the busdma sync operation, and
433 * disable SDCHI data interrrupts because we'll be driven by DMA
434 * interrupts (or SDHCI error interrupts) until the IO is done.
437 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
438 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
439 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
440 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
445 * Start the DMA transfer. Only programming errors (like failing to
446 * allocate a channel) cause a non-zero return from bcm_dma_start().
448 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
449 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
453 bcm_sdhci_dma_intr(int ch, void *arg)
455 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
456 struct sdhci_slot *slot = &sc->sc_slot;
460 mtx_lock(&slot->mtx);
463 * If there are more segments for the current dma, start the next one.
464 * Otherwise unload the dma map and decide what to do next based on the
465 * status of the sdhci controller and whether there's more data left.
467 if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
468 bcm_sdhci_start_dma_seg(sc);
469 mtx_unlock(&slot->mtx);
473 if (slot->curcmd->data->flags & MMC_DATA_READ) {
474 sync_op = BUS_DMASYNC_POSTREAD;
475 mask = SDHCI_INT_DATA_AVAIL;
477 sync_op = BUS_DMASYNC_POSTWRITE;
478 mask = SDHCI_INT_SPACE_AVAIL;
480 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
481 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
483 sc->dmamap_seg_count = 0;
484 sc->dmamap_seg_index = 0;
486 left = min(BCM_SDHCI_BUFFER_SIZE,
487 slot->curcmd->data->len - slot->offset);
490 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
492 if (reg & SDHCI_INT_DATA_END) {
493 /* ACK for all outstanding interrupts */
494 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
497 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
498 | SDHCI_INT_DATA_END;
499 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
502 /* finish this data */
503 sdhci_finish_data(slot);
506 /* already available? */
509 /* ACK for DATA_AVAIL or SPACE_AVAIL */
510 bcm_sdhci_write_4(slot->bus, slot,
511 SDHCI_INT_STATUS, mask);
513 /* continue next DMA transfer */
514 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
515 (uint8_t *)slot->curcmd->data->data +
516 slot->offset, left, bcm_sdhci_dmacb, sc,
517 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
518 slot->curcmd->error = MMC_ERR_NO_MEMORY;
519 sdhci_finish_data(slot);
521 bcm_sdhci_start_dma_seg(sc);
524 /* wait for next data by INT */
527 slot->intmask |= SDHCI_INT_DATA_AVAIL |
528 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
529 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
534 mtx_unlock(&slot->mtx);
538 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
540 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
543 if (sc->dmamap_seg_count != 0) {
544 device_printf(sc->sc_dev, "DMA in use\n");
548 left = min(BCM_SDHCI_BUFFER_SIZE,
549 slot->curcmd->data->len - slot->offset);
551 KASSERT((left & 3) == 0,
552 ("%s: len = %d, not word-aligned", __func__, left));
554 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
555 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
556 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
557 sc->dmamap_status != 0) {
558 slot->curcmd->error = MMC_ERR_NO_MEMORY;
563 bcm_sdhci_start_dma_seg(sc);
567 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
569 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
572 if (sc->dmamap_seg_count != 0) {
573 device_printf(sc->sc_dev, "DMA in use\n");
577 left = min(BCM_SDHCI_BUFFER_SIZE,
578 slot->curcmd->data->len - slot->offset);
580 KASSERT((left & 3) == 0,
581 ("%s: len = %d, not word-aligned", __func__, left));
583 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
584 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
585 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
586 sc->dmamap_status != 0) {
587 slot->curcmd->error = MMC_ERR_NO_MEMORY;
592 bcm_sdhci_start_dma_seg(sc);
596 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
601 * Do not use DMA for transfers less than block size or with a length
602 * that is not a multiple of four.
604 left = min(BCM_DMA_BLOCK_SIZE,
605 slot->curcmd->data->len - slot->offset);
606 if (left < BCM_DMA_BLOCK_SIZE)
615 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
619 /* DMA transfer FIFO 1KB */
620 if (slot->curcmd->data->flags & MMC_DATA_READ)
621 bcm_sdhci_read_dma(dev, slot);
623 bcm_sdhci_write_dma(dev, slot);
627 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
630 sdhci_finish_data(slot);
633 static device_method_t bcm_sdhci_methods[] = {
634 /* Device interface */
635 DEVMETHOD(device_probe, bcm_sdhci_probe),
636 DEVMETHOD(device_attach, bcm_sdhci_attach),
637 DEVMETHOD(device_detach, bcm_sdhci_detach),
640 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
641 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
642 DEVMETHOD(bus_print_child, bus_generic_print_child),
644 /* MMC bridge interface */
645 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
646 DEVMETHOD(mmcbr_request, sdhci_generic_request),
647 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
648 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
649 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
651 /* Platform transfer methods */
652 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
653 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
654 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
655 /* SDHCI registers accessors */
656 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
657 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
658 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
659 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
660 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
661 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
662 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
663 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
668 static devclass_t bcm_sdhci_devclass;
670 static driver_t bcm_sdhci_driver = {
673 sizeof(struct bcm_sdhci_softc),
676 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
677 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);