2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/mmc/bridge.h>
49 #include <dev/mmc/mmcreg.h>
50 #include <dev/mmc/mmcbrvar.h>
52 #include <dev/sdhci/sdhci.h>
55 #include "bcm2835_dma.h"
56 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
57 #include "bcm2835_vcbus.h"
59 #define BCM2835_DEFAULT_SDHCI_FREQ 50
61 #define BCM_SDHCI_BUFFER_SIZE 512
62 #define NUM_DMA_SEGS 2
65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
66 printf(fmt,##args); } while (0)
68 #define dprintf(fmt, args...)
71 static int bcm2835_sdhci_hs = 1;
72 static int bcm2835_sdhci_pio_mode = 0;
74 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
75 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
77 struct bcm_sdhci_softc {
80 struct resource * sc_mem_res;
81 struct resource * sc_irq_res;
82 bus_space_tag_t sc_bst;
83 bus_space_handle_t sc_bsh;
85 struct mmc_request * sc_req;
86 struct mmc_data * sc_data;
88 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
89 int sc_xfer_direction;
90 #define DIRECTION_READ 0
91 #define DIRECTION_WRITE 1
94 struct sdhci_slot sc_slot;
97 bus_dma_tag_t sc_dma_tag;
98 bus_dmamap_t sc_dma_map;
99 vm_paddr_t sc_sdhci_buffer_phys;
100 uint32_t cmd_and_mode;
101 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
102 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
103 int dmamap_seg_count;
104 int dmamap_seg_index;
108 static int bcm_sdhci_probe(device_t);
109 static int bcm_sdhci_attach(device_t);
110 static int bcm_sdhci_detach(device_t);
111 static void bcm_sdhci_intr(void *);
113 static int bcm_sdhci_get_ro(device_t, device_t);
114 static void bcm_sdhci_dma_intr(int ch, void *arg);
116 #define bcm_sdhci_lock(_sc) \
117 mtx_lock(&_sc->sc_mtx);
118 #define bcm_sdhci_unlock(_sc) \
119 mtx_unlock(&_sc->sc_mtx);
122 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
124 struct bcm_sdhci_softc *sc = arg;
127 sc->dmamap_status = err;
128 sc->dmamap_seg_count = nseg;
130 /* Note nseg is guaranteed to be zero if err is non-zero. */
131 for (i = 0; i < nseg; i++) {
132 sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
133 sc->dmamap_seg_sizes[i] = segs[i].ds_len;
138 bcm_sdhci_probe(device_t dev)
141 if (!ofw_bus_status_okay(dev))
144 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
147 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
148 return (BUS_PROBE_DEFAULT);
152 bcm_sdhci_attach(device_t dev)
154 struct bcm_sdhci_softc *sc = device_get_softc(dev);
163 err = bcm2835_mbox_set_power_state(dev, BCM2835_MBOX_POWER_ID_EMMC,
167 device_printf(dev, "Unable to enable the power\n");
172 err = bcm2835_mbox_get_clock_rate(dev, BCM2835_MBOX_CLOCK_ID_EMMC,
176 default_freq /= 1000000;
178 device_printf(dev, "default frequency: %dMHz\n",
181 if (default_freq == 0)
182 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
184 node = ofw_bus_get_node(sc->sc_dev);
185 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
186 default_freq = fdt32_to_cpu(cell)/1000000;
189 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
191 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
194 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
196 if (!sc->sc_mem_res) {
197 device_printf(dev, "cannot allocate memory window\n");
202 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
203 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
206 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
208 if (!sc->sc_irq_res) {
209 device_printf(dev, "cannot allocate interrupt\n");
214 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
215 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
216 device_printf(dev, "cannot setup interrupt handler\n");
221 if (!bcm2835_sdhci_pio_mode)
222 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
224 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
225 if (bcm2835_sdhci_hs)
226 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
227 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
228 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
229 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
230 | SDHCI_QUIRK_DONT_SET_HISPD_BIT
231 | SDHCI_QUIRK_MISSING_CAPS;
233 sdhci_init_slot(dev, &sc->sc_slot, 0);
235 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
236 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
237 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
238 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
239 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
240 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
243 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
245 /* Allocate bus_dma resources. */
246 err = bus_dma_tag_create(bus_get_dma_tag(dev),
247 1, 0, BUS_SPACE_MAXADDR_32BIT,
248 BUS_SPACE_MAXADDR, NULL, NULL,
249 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
250 BUS_DMA_ALLOCNOW, NULL, NULL,
254 device_printf(dev, "failed allocate DMA tag");
258 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
260 device_printf(dev, "bus_dmamap_create failed\n");
264 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
267 bus_generic_probe(dev);
268 bus_generic_attach(dev);
270 sdhci_start_slot(&sc->sc_slot);
276 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
278 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
280 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
281 mtx_destroy(&sc->sc_mtx);
287 bcm_sdhci_detach(device_t dev)
294 bcm_sdhci_intr(void *arg)
296 struct bcm_sdhci_softc *sc = arg;
298 sdhci_generic_intr(&sc->sc_slot);
302 bcm_sdhci_get_ro(device_t bus, device_t child)
308 static inline uint32_t
309 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
311 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
316 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
319 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
321 * The Arasan HC has a bug where it may lose the content of
322 * consecutive writes to registers that are within two SD-card
323 * clock cycles of each other (a clock domain crossing problem).
325 if (sc->sc_slot.clock > 0)
326 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
330 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
332 struct bcm_sdhci_softc *sc = device_get_softc(dev);
333 uint32_t val = RD4(sc, off & ~3);
335 return ((val >> (off & 3)*8) & 0xff);
339 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
341 struct bcm_sdhci_softc *sc = device_get_softc(dev);
342 uint32_t val = RD4(sc, off & ~3);
345 * Standard 32-bit handling of command and transfer mode.
347 if (off == SDHCI_TRANSFER_MODE) {
348 return (sc->cmd_and_mode >> 16);
349 } else if (off == SDHCI_COMMAND_FLAGS) {
350 return (sc->cmd_and_mode & 0x0000ffff);
352 return ((val >> (off & 3)*8) & 0xffff);
356 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
358 struct bcm_sdhci_softc *sc = device_get_softc(dev);
364 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
365 uint32_t *data, bus_size_t count)
367 struct bcm_sdhci_softc *sc = device_get_softc(dev);
369 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
373 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
375 struct bcm_sdhci_softc *sc = device_get_softc(dev);
376 uint32_t val32 = RD4(sc, off & ~3);
377 val32 &= ~(0xff << (off & 3)*8);
378 val32 |= (val << (off & 3)*8);
379 WR4(sc, off & ~3, val32);
383 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
385 struct bcm_sdhci_softc *sc = device_get_softc(dev);
387 if (off == SDHCI_COMMAND_FLAGS)
388 val32 = sc->cmd_and_mode;
390 val32 = RD4(sc, off & ~3);
391 val32 &= ~(0xffff << (off & 3)*8);
392 val32 |= (val << (off & 3)*8);
393 if (off == SDHCI_TRANSFER_MODE)
394 sc->cmd_and_mode = val32;
396 WR4(sc, off & ~3, val32);
397 if (off == SDHCI_COMMAND_FLAGS)
398 sc->cmd_and_mode = val32;
403 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
405 struct bcm_sdhci_softc *sc = device_get_softc(dev);
410 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
411 uint32_t *data, bus_size_t count)
413 struct bcm_sdhci_softc *sc = device_get_softc(dev);
415 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
419 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
421 struct sdhci_slot *slot;
422 vm_paddr_t pdst, psrc;
423 int err, idx, len, sync_op;
426 idx = sc->dmamap_seg_index++;
427 len = sc->dmamap_seg_sizes[idx];
430 if (slot->curcmd->data->flags & MMC_DATA_READ) {
431 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
432 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
433 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
435 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
436 psrc = sc->sc_sdhci_buffer_phys;
437 pdst = sc->dmamap_seg_addrs[idx];
438 sync_op = BUS_DMASYNC_PREREAD;
440 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
442 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
443 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
444 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
445 psrc = sc->dmamap_seg_addrs[idx];
446 pdst = sc->sc_sdhci_buffer_phys;
447 sync_op = BUS_DMASYNC_PREWRITE;
451 * When starting a new DMA operation do the busdma sync operation, and
452 * disable SDCHI data interrrupts because we'll be driven by DMA
453 * interrupts (or SDHCI error interrupts) until the IO is done.
456 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
457 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
458 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
459 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
464 * Start the DMA transfer. Only programming errors (like failing to
465 * allocate a channel) cause a non-zero return from bcm_dma_start().
467 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
468 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
472 bcm_sdhci_dma_intr(int ch, void *arg)
474 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
475 struct sdhci_slot *slot = &sc->sc_slot;
479 mtx_lock(&slot->mtx);
482 * If there are more segments for the current dma, start the next one.
483 * Otherwise unload the dma map and decide what to do next based on the
484 * status of the sdhci controller and whether there's more data left.
486 if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
487 bcm_sdhci_start_dma_seg(sc);
488 mtx_unlock(&slot->mtx);
492 if (slot->curcmd->data->flags & MMC_DATA_READ) {
493 sync_op = BUS_DMASYNC_POSTREAD;
494 mask = SDHCI_INT_DATA_AVAIL;
496 sync_op = BUS_DMASYNC_POSTWRITE;
497 mask = SDHCI_INT_SPACE_AVAIL;
499 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
500 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
502 sc->dmamap_seg_count = 0;
503 sc->dmamap_seg_index = 0;
505 left = min(BCM_SDHCI_BUFFER_SIZE,
506 slot->curcmd->data->len - slot->offset);
509 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
511 if (reg & SDHCI_INT_DATA_END) {
512 /* ACK for all outstanding interrupts */
513 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
516 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
517 | SDHCI_INT_DATA_END;
518 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
521 /* finish this data */
522 sdhci_finish_data(slot);
525 /* already available? */
528 /* ACK for DATA_AVAIL or SPACE_AVAIL */
529 bcm_sdhci_write_4(slot->bus, slot,
530 SDHCI_INT_STATUS, mask);
532 /* continue next DMA transfer */
533 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
534 (uint8_t *)slot->curcmd->data->data +
535 slot->offset, left, bcm_sdhci_dmacb, sc,
536 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
537 slot->curcmd->error = MMC_ERR_NO_MEMORY;
538 sdhci_finish_data(slot);
540 bcm_sdhci_start_dma_seg(sc);
543 /* wait for next data by INT */
546 slot->intmask |= SDHCI_INT_DATA_AVAIL |
547 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
548 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
553 mtx_unlock(&slot->mtx);
557 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
559 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
562 if (sc->dmamap_seg_count != 0) {
563 device_printf(sc->sc_dev, "DMA in use\n");
567 left = min(BCM_SDHCI_BUFFER_SIZE,
568 slot->curcmd->data->len - slot->offset);
570 KASSERT((left & 3) == 0,
571 ("%s: len = %d, not word-aligned", __func__, left));
573 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
574 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
575 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
576 sc->dmamap_status != 0) {
577 slot->curcmd->error = MMC_ERR_NO_MEMORY;
582 bcm_sdhci_start_dma_seg(sc);
586 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
588 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
591 if (sc->dmamap_seg_count != 0) {
592 device_printf(sc->sc_dev, "DMA in use\n");
596 left = min(BCM_SDHCI_BUFFER_SIZE,
597 slot->curcmd->data->len - slot->offset);
599 KASSERT((left & 3) == 0,
600 ("%s: len = %d, not word-aligned", __func__, left));
602 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
603 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
604 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
605 sc->dmamap_status != 0) {
606 slot->curcmd->error = MMC_ERR_NO_MEMORY;
611 bcm_sdhci_start_dma_seg(sc);
615 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
620 * Do not use DMA for transfers less than block size or with a length
621 * that is not a multiple of four.
623 left = min(BCM_DMA_BLOCK_SIZE,
624 slot->curcmd->data->len - slot->offset);
625 if (left < BCM_DMA_BLOCK_SIZE)
634 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
638 /* DMA transfer FIFO 1KB */
639 if (slot->curcmd->data->flags & MMC_DATA_READ)
640 bcm_sdhci_read_dma(dev, slot);
642 bcm_sdhci_write_dma(dev, slot);
646 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
649 sdhci_finish_data(slot);
652 static device_method_t bcm_sdhci_methods[] = {
653 /* Device interface */
654 DEVMETHOD(device_probe, bcm_sdhci_probe),
655 DEVMETHOD(device_attach, bcm_sdhci_attach),
656 DEVMETHOD(device_detach, bcm_sdhci_detach),
659 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
660 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
661 DEVMETHOD(bus_print_child, bus_generic_print_child),
663 /* MMC bridge interface */
664 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
665 DEVMETHOD(mmcbr_request, sdhci_generic_request),
666 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
667 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
668 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
670 /* Platform transfer methods */
671 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
672 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
673 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
674 /* SDHCI registers accessors */
675 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
676 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
677 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
678 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
679 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
680 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
681 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
682 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
687 static devclass_t bcm_sdhci_devclass;
689 static driver_t bcm_sdhci_driver = {
692 sizeof(struct bcm_sdhci_softc),
695 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
696 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);