2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/sysctl.h>
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 #include <machine/intr.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/spibus/spi.h>
50 #include <dev/spibus/spibusvar.h>
52 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
53 #include <arm/broadcom/bcm2835/bcm2835_spireg.h>
54 #include <arm/broadcom/bcm2835/bcm2835_spivar.h>
56 #include "spibus_if.h"
58 static struct ofw_compat_data compat_data[] = {
59 {"broadcom,bcm2835-spi", 1},
60 {"brcm,bcm2835-spi", 1},
64 static void bcm_spi_intr(void *);
68 bcm_spi_printr(device_t dev)
70 struct bcm_spi_softc *sc;
73 sc = device_get_softc(dev);
74 reg = BCM_SPI_READ(sc, SPI_CS);
75 device_printf(dev, "CS=%b\n", reg,
76 "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL"
77 "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN"
78 "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1"
79 "\30CSPOL2\31DMA_LEN\32LEN_LONG");
80 reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK;
85 device_printf(dev, "CLK=%uMhz/%d=%luhz\n",
86 SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg);
87 reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK;
88 device_printf(dev, "DLEN=%d\n", reg);
89 reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK;
90 device_printf(dev, "LTOH=%d\n", reg);
91 reg = BCM_SPI_READ(sc, SPI_DC);
92 device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n",
93 (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT,
94 (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT,
95 (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT,
96 (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT);
101 bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask,
106 mtx_assert(&sc->sc_mtx, MA_OWNED);
107 reg = BCM_SPI_READ(sc, off);
110 BCM_SPI_WRITE(sc, off, reg);
114 bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS)
116 struct bcm_spi_softc *sc;
120 sc = (struct bcm_spi_softc *)arg1;
123 clk = BCM_SPI_READ(sc, SPI_CLK);
128 clk = SPI_CORE_CLK / clk;
130 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req);
131 if (error != 0 || req->newptr == NULL)
134 clk = SPI_CORE_CLK / clk;
142 BCM_SPI_WRITE(sc, SPI_CLK, clk);
149 bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit)
151 struct bcm_spi_softc *sc;
155 sc = (struct bcm_spi_softc *)arg1;
157 reg = BCM_SPI_READ(sc, SPI_CS);
159 reg = (reg & bit) ? 1 : 0;
161 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
162 if (error != 0 || req->newptr == NULL)
168 bcm_spi_modifyreg(sc, SPI_CS, bit, reg);
175 bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS)
178 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL));
182 bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS)
185 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA));
189 bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS)
192 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0));
196 bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS)
199 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1));
203 bcm_spi_sysctl_init(struct bcm_spi_softc *sc)
205 struct sysctl_ctx_list *ctx;
206 struct sysctl_oid *tree_node;
207 struct sysctl_oid_list *tree;
210 * Add system sysctl tree/handlers.
212 ctx = device_get_sysctl_ctx(sc->sc_dev);
213 tree_node = device_get_sysctl_tree(sc->sc_dev);
214 tree = SYSCTL_CHILDREN(tree_node);
215 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock",
216 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
217 bcm_spi_clock_proc, "IU", "SPI BUS clock frequency");
218 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol",
219 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
220 bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity");
221 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha",
222 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
223 bcm_spi_cpha_proc, "IU", "SPI BUS clock phase");
224 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0",
225 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
226 bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity");
227 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1",
228 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
229 bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity");
233 bcm_spi_probe(device_t dev)
236 if (!ofw_bus_status_okay(dev))
239 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
242 device_set_desc(dev, "BCM2708/2835 SPI controller");
244 return (BUS_PROBE_DEFAULT);
248 bcm_spi_attach(device_t dev)
250 struct bcm_spi_softc *sc;
254 if (device_get_unit(dev) != 0) {
255 device_printf(dev, "only one SPI controller supported\n");
259 sc = device_get_softc(dev);
262 /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */
263 gpio = devclass_get_device(devclass_find("gpio"), 0);
265 device_printf(dev, "cannot find gpio0\n");
268 for (i = 0; i < nitems(bcm_spi_pins); i++)
269 bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0);
272 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
274 if (!sc->sc_mem_res) {
275 device_printf(dev, "cannot allocate memory window\n");
279 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
280 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
283 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
285 if (!sc->sc_irq_res) {
286 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
287 device_printf(dev, "cannot allocate interrupt\n");
291 /* Hook up our interrupt handler. */
292 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
293 NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) {
294 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
295 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
296 device_printf(dev, "cannot setup the interrupt handler\n");
300 mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF);
302 /* Add sysctl nodes. */
303 bcm_spi_sysctl_init(sc);
310 * Enable the SPI controller. Clear the rx and tx FIFO.
311 * Defaults to SPI mode 0.
313 BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
315 /* Set the SPI clock to 500Khz. */
316 BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000);
322 device_add_child(dev, "spibus", -1);
324 return (bus_generic_attach(dev));
328 bcm_spi_detach(device_t dev)
330 struct bcm_spi_softc *sc;
332 bus_generic_detach(dev);
334 sc = device_get_softc(dev);
335 mtx_destroy(&sc->sc_mtx);
337 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
339 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
341 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
347 bcm_spi_fill_fifo(struct bcm_spi_softc *sc)
349 struct spi_command *cmd;
350 uint32_t cs, written;
354 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
355 while (sc->sc_written < sc->sc_len &&
356 cs == (SPI_CS_TA | SPI_CS_TXD)) {
357 data = (uint8_t *)cmd->tx_cmd;
358 written = sc->sc_written++;
359 if (written >= cmd->tx_cmd_sz) {
360 data = (uint8_t *)cmd->tx_data;
361 written -= cmd->tx_cmd_sz;
363 BCM_SPI_WRITE(sc, SPI_FIFO, data[written]);
364 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
369 bcm_spi_drain_fifo(struct bcm_spi_softc *sc)
371 struct spi_command *cmd;
376 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
377 while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) {
378 data = (uint8_t *)cmd->rx_cmd;
379 read = sc->sc_read++;
380 if (read >= cmd->rx_cmd_sz) {
381 data = (uint8_t *)cmd->rx_data;
382 read -= cmd->rx_cmd_sz;
384 data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff;
385 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
390 bcm_spi_intr(void *arg)
392 struct bcm_spi_softc *sc;
394 sc = (struct bcm_spi_softc *)arg;
397 /* Filter stray interrupts. */
398 if ((sc->sc_flags & BCM_SPI_BUSY) == 0) {
403 /* TX - Fill up the FIFO. */
404 bcm_spi_fill_fifo(sc);
406 /* RX - Drain the FIFO. */
407 bcm_spi_drain_fifo(sc);
409 /* Check for end of transfer. */
410 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
411 /* Disable interrupts and the SPI engine. */
412 bcm_spi_modifyreg(sc, SPI_CS,
413 SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
421 bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
423 struct bcm_spi_softc *sc;
427 sc = device_get_softc(dev);
429 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
430 ("TX/RX command sizes should be equal"));
431 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
432 ("TX/RX data sizes should be equal"));
434 /* Get the proper chip select for this child. */
435 spibus_get_cs(child, &cs);
437 cs &= ~SPIBUS_CS_HIGH;
441 "Invalid chip select %d requested by %s\n", cs,
442 device_get_nameunit(child));
448 /* If the controller is in use wait until it is available. */
449 while (sc->sc_flags & BCM_SPI_BUSY)
450 mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0);
452 /* Now we have control over SPI controller. */
453 sc->sc_flags = BCM_SPI_BUSY;
455 /* Clear the FIFO. */
456 bcm_spi_modifyreg(sc, SPI_CS,
457 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO,
458 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
460 /* Save a pointer to the SPI command. */
464 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
467 * Set the CS for this transaction, enable interrupts and announce
468 * we're ready to tx. This will kick off the first interrupt.
470 bcm_spi_modifyreg(sc, SPI_CS,
471 SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD,
472 cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD);
474 /* Wait for the transaction to complete. */
475 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2);
477 /* Make sure the SPI engine and interrupts are disabled. */
478 bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
480 /* Release the controller and wakeup the next thread waiting for it. */
486 * Check for transfer timeout. The SPI controller doesn't
489 if (err == EWOULDBLOCK) {
490 device_printf(sc->sc_dev, "SPI error\n");
498 bcm_spi_get_node(device_t bus, device_t dev)
501 /* We only have one child, the SPI bus, which needs our own node. */
502 return (ofw_bus_get_node(bus));
505 static device_method_t bcm_spi_methods[] = {
506 /* Device interface */
507 DEVMETHOD(device_probe, bcm_spi_probe),
508 DEVMETHOD(device_attach, bcm_spi_attach),
509 DEVMETHOD(device_detach, bcm_spi_detach),
512 DEVMETHOD(spibus_transfer, bcm_spi_transfer),
514 /* ofw_bus interface */
515 DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node),
520 static devclass_t bcm_spi_devclass;
522 static driver_t bcm_spi_driver = {
525 sizeof(struct bcm_spi_softc),
528 DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0);