2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
3 * Copyright (c) 2012, 2013 The FreeBSD Foundation
6 * Portions of this software were developed by Oleksandr Rybalko
7 * under sponsorship from the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/resource.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
46 #include <sys/mutex.h>
48 #include <dev/iicbus/iiconf.h>
49 #include <dev/iicbus/iicbus.h>
50 #include "iicbus_if.h"
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
57 #define I2C_ADDR_REG 0x00 /* I2C slave address register */
58 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */
59 #define I2C_CONTROL_REG 0x08 /* I2C control register */
60 #define I2C_STATUS_REG 0x0C /* I2C status register */
61 #define I2C_DATA_REG 0x10 /* I2C data register */
62 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */
64 #define I2CCR_MEN (1 << 7) /* Module enable */
65 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */
66 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */
67 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */
68 #define I2CCR_RSTA (1 << 2) /* Repeated START */
70 #define I2CSR_MCF (1 << 7) /* Data transfer */
71 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */
72 #define I2CSR_MBB (1 << 5) /* Bus busy */
73 #define I2CSR_MAL (1 << 4) /* Arbitration lost */
74 #define I2CSR_SRW (1 << 2) /* Slave read/write */
75 #define I2CSR_MIF (1 << 1) /* Module interrupt */
76 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */
78 #define I2C_BAUD_RATE_FAST 0x31
79 #define I2C_BAUD_RATE_DEF 0x3F
80 #define I2C_DFSSR_DIV 0x10
83 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
84 printf(fmt,##args); } while (0)
86 #define debugf(fmt, args...)
95 bus_space_handle_t bsh;
99 static phandle_t i2c_get_node(device_t, device_t);
100 static int i2c_probe(device_t);
101 static int i2c_attach(device_t);
103 static int i2c_repeated_start(device_t, u_char, int);
104 static int i2c_start(device_t, u_char, int);
105 static int i2c_stop(device_t);
106 static int i2c_reset(device_t, u_char, u_char, u_char *);
107 static int i2c_read(device_t, char *, int, int *, int, int);
108 static int i2c_write(device_t, const char *, int, int *, int);
110 static device_method_t i2c_methods[] = {
111 DEVMETHOD(device_probe, i2c_probe),
112 DEVMETHOD(device_attach, i2c_attach),
115 DEVMETHOD(ofw_bus_get_node, i2c_get_node),
117 DEVMETHOD(iicbus_callback, iicbus_null_callback),
118 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
119 DEVMETHOD(iicbus_start, i2c_start),
120 DEVMETHOD(iicbus_stop, i2c_stop),
121 DEVMETHOD(iicbus_reset, i2c_reset),
122 DEVMETHOD(iicbus_read, i2c_read),
123 DEVMETHOD(iicbus_write, i2c_write),
124 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
129 static driver_t i2c_driver = {
132 sizeof(struct i2c_softc),
134 static devclass_t i2c_devclass;
136 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
137 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
140 i2c_get_node(device_t bus, device_t dev)
143 * Share controller node with iicbus device
145 return ofw_bus_get_node(bus);
149 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val)
152 bus_space_write_1(sc->bst, sc->bsh, off, val);
155 static __inline uint8_t
156 i2c_read_reg(struct i2c_softc *sc, bus_size_t off)
159 return (bus_space_read_1(sc->bst, sc->bsh, off));
163 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask)
167 status = i2c_read_reg(sc, off);
169 i2c_write_reg(sc, off, status);
172 /* Wait for transfer interrupt flag */
174 wait_for_iif(struct i2c_softc *sc)
180 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MIF)
185 return (IIC_ETIMEOUT);
188 /* Wait for free bus */
190 wait_for_nibb(struct i2c_softc *sc)
196 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0)
201 return (IIC_ETIMEOUT);
204 /* Wait for transfer complete+interrupt flag */
206 wait_for_icf(struct i2c_softc *sc)
213 if ((i2c_read_reg(sc, I2C_STATUS_REG) &
214 (I2CSR_MCF|I2CSR_MIF)) == (I2CSR_MCF|I2CSR_MIF))
219 return (IIC_ETIMEOUT);
223 i2c_probe(device_t dev)
225 struct i2c_softc *sc;
227 if (!ofw_bus_is_compatible(dev, "fsl,imx-i2c"))
230 sc = device_get_softc(dev);
233 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
235 if (sc->res == NULL) {
236 device_printf(dev, "could not allocate resources\n");
240 sc->bst = rman_get_bustag(sc->res);
241 sc->bsh = rman_get_bushandle(sc->res);
244 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
245 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
246 device_set_desc(dev, "I2C bus controller");
248 return (BUS_PROBE_DEFAULT);
252 i2c_attach(device_t dev)
254 struct i2c_softc *sc;
256 sc = device_get_softc(dev);
260 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
262 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
264 if (sc->res == NULL) {
265 device_printf(dev, "could not allocate resources");
266 mtx_destroy(&sc->mutex);
270 sc->bst = rman_get_bustag(sc->res);
271 sc->bsh = rman_get_bushandle(sc->res);
273 sc->iicbus = device_add_child(dev, "iicbus", -1);
274 if (sc->iicbus == NULL) {
275 device_printf(dev, "could not add iicbus child");
276 mtx_destroy(&sc->mutex);
280 bus_generic_attach(dev);
285 i2c_repeated_start(device_t dev, u_char slave, int timeout)
287 struct i2c_softc *sc;
290 sc = device_get_softc(dev);
292 mtx_lock(&sc->mutex);
294 i2c_write_reg(sc, I2C_ADDR_REG, slave);
295 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) {
296 mtx_unlock(&sc->mutex);
297 return (IIC_EBUSBSY);
300 /* Set repeated start condition */
302 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA);
305 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
306 /* Write target address - LSB is R/W bit */
307 i2c_write_reg(sc, I2C_DATA_REG, slave);
309 error = wait_for_iif(sc);
312 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
314 mtx_unlock(&sc->mutex);
323 i2c_start(device_t dev, u_char slave, int timeout)
325 struct i2c_softc *sc;
328 sc = device_get_softc(dev);
330 mtx_lock(&sc->mutex);
331 i2c_write_reg(sc, I2C_ADDR_REG, slave);
332 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) {
333 mtx_unlock(&sc->mutex);
334 return (IIC_EBUSBSY);
337 /* Set start condition */
338 i2c_write_reg(sc, I2C_CONTROL_REG,
339 I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK);
341 i2c_write_reg(sc, I2C_CONTROL_REG,
342 I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX | I2CCR_TXAK);
344 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
345 /* Write target address - LSB is R/W bit */
346 i2c_write_reg(sc, I2C_DATA_REG, slave);
348 error = wait_for_iif(sc);
350 mtx_unlock(&sc->mutex);
359 i2c_stop(device_t dev)
361 struct i2c_softc *sc;
363 sc = device_get_softc(dev);
364 mtx_lock(&sc->mutex);
365 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK);
367 /* Reset controller if bus still busy after STOP */
368 if (wait_for_nibb(sc) == IIC_ETIMEOUT) {
369 i2c_write_reg(sc, I2C_CONTROL_REG, 0);
371 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK);
373 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
375 mtx_unlock(&sc->mutex);
381 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
383 struct i2c_softc *sc;
386 sc = device_get_softc(dev);
390 baud_rate = I2C_BAUD_RATE_FAST;
396 baud_rate = I2C_BAUD_RATE_DEF;
400 mtx_lock(&sc->mutex);
401 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
402 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
405 i2c_write_reg(sc, I2C_FDR_REG, 20);
406 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
408 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
409 mtx_unlock(&sc->mutex);
415 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
417 struct i2c_softc *sc;
420 sc = device_get_softc(dev);
423 mtx_lock(&sc->mutex);
427 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
428 I2CCR_MSTA | I2CCR_TXAK);
431 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
435 i2c_read_reg(sc, I2C_DATA_REG);
439 while (*read < len) {
440 error = wait_for_icf(sc);
442 mtx_unlock(&sc->mutex);
445 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
446 if ((*read == len - 2) && last) {
447 /* NO ACK on last byte */
448 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
449 I2CCR_MSTA | I2CCR_TXAK);
452 if ((*read == len - 1) && last) {
453 /* Transfer done, remove master bit */
454 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
458 reg = i2c_read_reg(sc, I2C_DATA_REG);
462 mtx_unlock(&sc->mutex);
468 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
470 struct i2c_softc *sc;
473 sc = device_get_softc(dev);
476 mtx_lock(&sc->mutex);
477 while (*sent < len) {
478 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
479 i2c_write_reg(sc, I2C_DATA_REG, *buf++);
481 error = wait_for_iif(sc);
483 mtx_unlock(&sc->mutex);
489 mtx_unlock(&sc->mutex);