2 * Copyright (c) 2017 Rogiel Sulzbach <rogiel@allogica.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
38 #include <machine/bus.h>
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
42 #include <dev/ahci/ahci.h>
43 #include <arm/freescale/imx/imx_iomuxreg.h>
44 #include <arm/freescale/imx/imx_iomuxvar.h>
45 #include <arm/freescale/imx/imx_ccmvar.h>
47 #define SATA_TIMER1MS 0x000000e0
49 #define SATA_P0PHYCR 0x00000178
50 #define SATA_P0PHYCR_CR_READ (1 << 19)
51 #define SATA_P0PHYCR_CR_WRITE (1 << 18)
52 #define SATA_P0PHYCR_CR_CAP_DATA (1 << 17)
53 #define SATA_P0PHYCR_CR_CAP_ADDR (1 << 16)
54 #define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff)
56 #define SATA_P0PHYSR 0x0000017c
57 #define SATA_P0PHYSR_CR_ACK (1 << 18)
58 #define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff)
61 #define SATA_PHY_CLOCK_RESET 0x7f3f
62 #define SATA_PHY_CLOCK_RESET_RST (1 << 0)
64 #define SATA_PHY_LANE0_OUT_STAT 0x2003
65 #define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE (1 << 1)
68 imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, bool on)
74 v = ATA_INL(sc->r_mem, SATA_P0PHYCR);
80 ATA_OUTL(sc->r_mem, SATA_P0PHYCR, v);
82 for (timeout = 5000; timeout > 0; --timeout) {
83 v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
84 state = (v & SATA_P0PHYSR_CR_ACK) == SATA_P0PHYSR_CR_ACK;
99 imx6_ahci_phy_addr(struct ahci_controller* sc, uint32_t addr)
105 ATA_OUTL(sc->r_mem, SATA_P0PHYCR, addr);
107 error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, true);
109 device_printf(sc->dev,
110 "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n",
115 error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, false);
117 device_printf(sc->dev,
118 "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n",
127 imx6_ahci_phy_write(struct ahci_controller* sc, uint32_t addr,
132 error = imx6_ahci_phy_addr(sc, addr);
134 device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
139 ATA_OUTL(sc->r_mem, SATA_P0PHYCR, data);
141 error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, true);
143 device_printf(sc->dev,
144 "%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__);
147 if (imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, false) != 0) {
148 device_printf(sc->dev,
149 "%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__);
153 if ((addr == SATA_PHY_CLOCK_RESET) && data) {
154 /* we can't check ACK after RESET */
155 ATA_OUTL(sc->r_mem, SATA_P0PHYCR,
156 SATA_P0PHYCR_CR_DATA_IN(data) | SATA_P0PHYCR_CR_WRITE);
160 error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, true);
162 device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n",
167 error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, false);
169 device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n",
178 imx6_ahci_phy_read(struct ahci_controller* sc, uint32_t addr, uint16_t* val)
183 error = imx6_ahci_phy_addr(sc, addr);
185 device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
190 error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, true);
192 device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=1\n",
197 v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
199 error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, false);
201 device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=0\n",
206 *val = SATA_P0PHYSR_CR_DATA_OUT(v);
211 imx6_ahci_probe(device_t dev)
214 if (!ofw_bus_status_okay(dev)) {
218 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ahci")) {
221 device_set_desc(dev, "i.MX6 Integrated AHCI controller");
223 return (BUS_PROBE_DEFAULT);
227 imx6_ahci_attach(device_t dev)
229 struct ahci_controller* ctlr;
234 ctlr = device_get_softc(dev);
236 /* Power up the controller and phy. */
237 error = imx6_ccm_sata_enable();
239 device_printf(dev, "error enabling controller and phy\n");
245 ctlr->subvendorid = 0;
246 ctlr->subdeviceid = 0;
249 if ((ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
250 &ctlr->r_rid, RF_ACTIVE)) == NULL) {
254 v = imx_iomux_gpr_get(IOMUX_GPR13);
255 /* Clear out existing values; these numbers are bitmasks. */
256 v &= ~(IOMUX_GPR13_SATA_PHY_8(7) |
257 IOMUX_GPR13_SATA_PHY_7(0x1f) |
258 IOMUX_GPR13_SATA_PHY_6(7) |
259 IOMUX_GPR13_SATA_SPEED(1) |
260 IOMUX_GPR13_SATA_PHY_5(1) |
261 IOMUX_GPR13_SATA_PHY_4(7) |
262 IOMUX_GPR13_SATA_PHY_3(0xf) |
263 IOMUX_GPR13_SATA_PHY_2(0x1f) |
264 IOMUX_GPR13_SATA_PHY_1(1) |
265 IOMUX_GPR13_SATA_PHY_0(1));
267 v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */
268 IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */
269 IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */
270 IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */
271 IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */
272 IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */
273 IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */
274 IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */
275 IOMUX_GPR13_SATA_PHY_1(1); /* PLL clock enable */
276 imx_iomux_gpr_set(IOMUX_GPR13, v);
279 error = imx6_ahci_phy_write(ctlr, SATA_PHY_CLOCK_RESET,
280 SATA_PHY_CLOCK_RESET_RST);
282 device_printf(dev, "cannot reset PHY\n");
286 for (timeout = 50; timeout > 0; --timeout) {
288 error = imx6_ahci_phy_read(ctlr, SATA_PHY_LANE0_OUT_STAT,
291 device_printf(dev, "cannot read LANE0 status\n");
294 if (pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE) {
299 device_printf(dev, "time out reading LANE0 status\n");
304 /* Support Staggered Spin-up */
305 v = ATA_INL(ctlr->r_mem, AHCI_CAP);
306 ATA_OUTL(ctlr->r_mem, AHCI_CAP, v | AHCI_CAP_SSS);
308 /* Ports Implemented. must set 1 */
309 v = ATA_INL(ctlr->r_mem, AHCI_PI);
310 ATA_OUTL(ctlr->r_mem, AHCI_PI, v | (1 << 0));
312 /* set 1ms-timer = AHB clock / 1000 */
313 ATA_OUTL(ctlr->r_mem, SATA_TIMER1MS,
314 imx_ccm_ahb_hz() / 1000);
317 * Note: ahci_attach will release ctlr->r_mem on errors automatically
319 return (ahci_attach(dev));
322 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
327 imx6_ahci_detach(device_t dev)
330 return (ahci_detach(dev));
333 static device_method_t imx6_ahci_ata_methods[] = {
334 /* device probe, attach and detach methods */
335 DEVMETHOD(device_probe, imx6_ahci_probe),
336 DEVMETHOD(device_attach, imx6_ahci_attach),
337 DEVMETHOD(device_detach, imx6_ahci_detach),
339 /* ahci bus methods */
340 DEVMETHOD(bus_print_child, ahci_print_child),
341 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
342 DEVMETHOD(bus_release_resource, ahci_release_resource),
343 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
344 DEVMETHOD(bus_teardown_intr, ahci_teardown_intr),
345 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
350 static driver_t ahci_ata_driver = {
352 imx6_ahci_ata_methods,
353 sizeof(struct ahci_controller)
356 DRIVER_MODULE(imx6_ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0);