2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs.
35 * Also, temperature montoring and cpu frequency control. It was Freescale who
36 * kitchen-sinked this device, not us. :)
38 * We don't really do anything with analog PLLs, but the registers for
39 * controlling them belong to the same block as the power regulator registers.
40 * Since the newbus hierarchy makes it hard for anyone other than us to get at
41 * them, we just export a couple public functions to allow the imx6 CCM clock
42 * driver to read and write those registers.
44 * We also don't do anything about power regulation yet, but when the need
45 * arises, this would be the place for that code to live.
47 * I have no idea where the "anatop" name comes from. It's in the standard DTS
48 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
49 * from Freescale, but it's not in the SoC manual.
51 * Note that temperature values throughout this code are handled in two types of
52 * units. Items with '_cnt' in the name use the hardware temperature count
53 * units (higher counts are lower temperatures). Items with '_val' in the name
54 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl
55 * handlers (dK is the standard unit for temperature in sysctl).
58 #include <sys/param.h>
59 #include <sys/systm.h>
60 #include <sys/callout.h>
61 #include <sys/kernel.h>
62 #include <sys/limits.h>
63 #include <sys/sysctl.h>
64 #include <sys/module.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
71 #include <machine/bus.h>
73 #include <arm/arm/mpcore_timervar.h>
74 #include <arm/freescale/fsl_ocotpreg.h>
75 #include <arm/freescale/fsl_ocotpvar.h>
76 #include <arm/freescale/imx/imx_ccmvar.h>
77 #include <arm/freescale/imx/imx_machdep.h>
78 #include <arm/freescale/imx/imx6_anatopreg.h>
79 #include <arm/freescale/imx/imx6_anatopvar.h>
81 static struct resource_spec imx6_anatop_spec[] = {
82 { SYS_RES_MEMORY, 0, RF_ACTIVE },
88 struct imx6_anatop_softc {
90 struct resource *res[2];
91 struct intr_config_hook
99 uint32_t cpu_maxmhz_hw;
100 boolean_t cpu_overclock_enable;
101 boolean_t cpu_init_done;
104 uint32_t temp_high_val;
105 uint32_t temp_high_cnt;
106 uint32_t temp_last_cnt;
107 uint32_t temp_room_cnt;
108 struct callout temp_throttle_callout;
109 sbintime_t temp_throttle_delay;
110 uint32_t temp_throttle_reset_cnt;
111 uint32_t temp_throttle_trigger_cnt;
112 uint32_t temp_throttle_val;
115 static struct imx6_anatop_softc *imx6_anatop_sc;
118 * Table of "operating points".
119 * These are combinations of frequency and voltage blessed by Freescale.
120 * While the datasheet says the ARM voltage can be as low as 925mV at
121 * 396MHz, it also says that the ARM and SOC voltages can't differ by
122 * more than 200mV, and the minimum SOC voltage is 1150mV, so that
123 * dictates the 950mV entry in this table.
128 } imx6_oppt_table[] = {
137 * Table of CPU max frequencies. This is used to translate the max frequency
138 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
139 * up in the operating points table.
141 static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200};
143 #define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celcius offset. */
146 imx6_anatop_read_4(bus_size_t offset)
149 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL"));
151 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset));
155 imx6_anatop_write_4(bus_size_t offset, uint32_t value)
158 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL"));
160 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);
164 vdd_set(struct imx6_anatop_softc *sc, int mv)
166 int newtarg, newtargSoc, oldtarg;
167 uint32_t delay, pmureg;
168 static boolean_t init_done = false;
171 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM
172 * can't be more than 50mV above or 200mV below them. We keep them the
173 * same except in the case of the lowest operating point, which is
174 * handled as a special case below.
177 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE);
178 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK;
180 /* Convert mV to target value. Clamp target to valid range. */
186 newtarg = (mv - 700) / 25;
189 * The SOC voltage can't go below 1150mV, and thus because of the 200mV
190 * rule, the ARM voltage can't go below 950mV. The 950 is encoded in
191 * our oppt table, here we handle the SOC 1150 rule as a special case.
194 newtargSoc = (newtarg < 18) ? 18 : newtarg;
197 * The first time through the 3 voltages might not be equal so use a
198 * long conservative delay. After that we need to delay 3uS for every
199 * 25mV step upward; we actually delay 6uS because empirically, it works
200 * and the 3uS per step recommended by the docs doesn't (3uS fails when
201 * going from 400->1200, but works for smaller changes).
204 if (newtarg == oldtarg)
206 else if (newtarg > oldtarg)
207 delay = (newtarg - oldtarg) * 6;
211 delay = (700 / 25) * 6;
216 * Make the change and wait for it to take effect.
218 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK |
219 IMX6_ANALOG_PMU_REG1_TARG_MASK |
220 IMX6_ANALOG_PMU_REG2_TARG_MASK);
222 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT;
223 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT;
224 pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT;
226 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg);
228 sc->cpu_curmv = newtarg * 25 + 700;
231 static inline uint32_t
232 cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t corediv,
236 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1));
240 cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz,
241 uint32_t *corediv, uint32_t *plldiv)
244 *corediv = (cpu_mhz < 650) ? 1 : 0;
245 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2);
248 static inline uint32_t
249 cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz)
251 uint32_t corediv, plldiv;
253 cpufreq_mhz_to_div(sc, cpu_mhz, &corediv, &plldiv);
254 return (cpufreq_mhz_from_div(sc, corediv, plldiv));
258 cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz)
260 int d, diff, i, nearest;
262 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable)
263 cpu_newmhz = sc->cpu_maxmhz_hw;
267 for (i = 0; i < nitems(imx6_oppt_table); ++i) {
268 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz);
274 return (&imx6_oppt_table[nearest]);
278 cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op)
280 uint32_t corediv, plldiv, timeout, wrk32;
282 /* If increasing the frequency, we must first increase the voltage. */
283 if (op->mhz > sc->cpu_curmhz) {
288 * I can't find a documented procedure for changing the ARM PLL divisor,
289 * but some trial and error came up with this:
290 * - Set the bypass clock source to REF_CLK_24M (source #0).
291 * - Set the PLL into bypass mode; cpu should now be running at 24mhz.
292 * - Change the divisor.
293 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations.
294 * - Turn off bypass mode; cpu should now be running at the new speed.
296 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv);
297 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
298 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK);
299 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET,
300 IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
302 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM);
303 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
305 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32);
308 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
309 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0)
311 panic("imx6_set_cpu_clock(): PLL never locked");
313 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
314 IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
315 imx_ccm_set_cacrr(corediv);
317 /* If lowering the frequency, it is now safe to lower the voltage. */
318 if (op->mhz < sc->cpu_curmhz)
320 sc->cpu_curmhz = op->mhz;
322 /* Tell the mpcore timer that its frequency has changed. */
323 arm_tmr_change_frequency(
324 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2);
328 cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS)
330 struct imx6_anatop_softc *sc;
337 temp = sc->cpu_minmhz;
338 err = sysctl_handle_int(oidp, &temp, 0, req);
339 if (err != 0 || req->newptr == NULL)
342 op = cpufreq_nearest_oppt(sc, temp);
343 if (op->mhz > sc->cpu_maxmhz)
345 else if (op->mhz == sc->cpu_minmhz)
349 * Value changed, update softc. If the new min is higher than the
350 * current speed, raise the current speed to match.
352 sc->cpu_minmhz = op->mhz;
353 if (sc->cpu_minmhz > sc->cpu_curmhz) {
354 cpufreq_set_clock(sc, op);
360 cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS)
362 struct imx6_anatop_softc *sc;
369 temp = sc->cpu_maxmhz;
370 err = sysctl_handle_int(oidp, &temp, 0, req);
371 if (err != 0 || req->newptr == NULL)
374 op = cpufreq_nearest_oppt(sc, temp);
375 if (op->mhz < sc->cpu_minmhz)
377 else if (op->mhz == sc->cpu_maxmhz)
381 * Value changed, update softc and hardware. The hardware update is
382 * unconditional. We always try to run at max speed, so any change of
383 * the max means we need to change the current speed too, regardless of
384 * whether it is higher or lower than the old max.
386 sc->cpu_maxmhz = op->mhz;
387 cpufreq_set_clock(sc, op);
393 cpufreq_initialize(struct imx6_anatop_softc *sc)
398 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
399 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0,
402 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
403 OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
404 sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency");
406 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
407 OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
408 sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency");
410 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
411 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0,
412 "Maximum CPU frequency allowed by hardware");
414 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
415 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN,
416 &sc->cpu_overclock_enable, 0,
417 "Allow setting CPU frequency higher than cpu_maxmhz_hw");
420 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm
421 * (even though in the real world it will always be 24mhz). Oh wait a
422 * sec, I never wrote imx6_ccm.
427 * Get the maximum speed this cpu can be set to. The values in the
428 * OCOTP CFG3 register are not documented in the reference manual.
429 * The following info was in an archived email found via web search:
430 * - 2b'11: 1200000000Hz;
431 * - 2b'10: 996000000Hz;
432 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
433 * - 2b'00: 792000000Hz;
434 * The default hardware max speed can be overridden by a tunable.
436 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) &
437 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT;
438 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed];
439 sc->cpu_maxmhz = sc->cpu_maxmhz_hw;
441 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz);
442 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz);
443 sc->cpu_minmhz = op->mhz;
444 sc->cpu_minmv = op->mv;
446 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz);
447 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz);
448 sc->cpu_maxmhz = op->mhz;
449 sc->cpu_maxmv = op->mv;
452 * Set the CPU to maximum speed.
454 * We won't have thermal throttling until interrupts are enabled, but we
455 * want to run at full speed through all the device init stuff. This
456 * basically assumes that a single core can't overheat before interrupts
457 * are enabled; empirical testing shows that to be a safe assumption.
459 cpufreq_set_clock(sc, op);
462 static inline uint32_t
463 temp_from_count(struct imx6_anatop_softc *sc, uint32_t count)
466 return (((sc->temp_high_val - (count - sc->temp_high_cnt) *
467 (sc->temp_high_val - 250) /
468 (sc->temp_room_cnt - sc->temp_high_cnt))));
471 static inline uint32_t
472 temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp)
475 return ((sc->temp_room_cnt - sc->temp_high_cnt) *
476 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) +
481 temp_update_count(struct imx6_anatop_softc *sc)
485 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0);
486 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID))
489 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >>
490 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT;
494 temp_sysctl_handler(SYSCTL_HANDLER_ARGS)
496 struct imx6_anatop_softc *sc = arg1;
499 temp_update_count(sc);
501 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC;
503 return (sysctl_handle_int(oidp, &t, 0, req));
507 temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS)
509 struct imx6_anatop_softc *sc = arg1;
513 temp = sc->temp_throttle_val + TZ_ZEROC;
514 err = sysctl_handle_int(oidp, &temp, 0, req);
518 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val)
521 /* Value changed, update counts in softc and hardware. */
522 sc->temp_throttle_val = temp;
523 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val);
524 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100);
525 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR,
526 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK);
527 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET,
528 (sc->temp_throttle_trigger_cnt <<
529 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT));
534 tempmon_gofast(struct imx6_anatop_softc *sc)
537 if (sc->cpu_curmhz < sc->cpu_maxmhz) {
538 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz));
543 tempmon_goslow(struct imx6_anatop_softc *sc)
546 if (sc->cpu_curmhz > sc->cpu_minmhz) {
547 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz));
552 tempmon_intr(void *arg)
554 struct imx6_anatop_softc *sc = arg;
557 * XXX Note that this code doesn't currently run (for some mysterious
558 * reason we just never get an interrupt), so the real monitoring is
559 * done by tempmon_throttle_check().
562 /* XXX Schedule callout to speed back up eventually. */
563 return (FILTER_HANDLED);
567 tempmon_throttle_check(void *arg)
569 struct imx6_anatop_softc *sc = arg;
571 /* Lower counts are higher temperatures. */
572 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt)
574 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt))
577 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
578 0, tempmon_throttle_check, sc, 0);
583 initialize_tempmon(struct imx6_anatop_softc *sc)
588 * Fetch calibration data: a sensor count at room temperature (25C),
589 * a sensor count at a high temperature, and that temperature
591 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1);
592 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20;
593 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8;
594 sc->temp_high_val = (cal & 0x000000FF) * 10;
597 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and
598 * reset back to max cpu freq at 5C below the trigger.
600 sc->temp_throttle_val = sc->temp_high_val - 100;
601 sc->temp_throttle_trigger_cnt =
602 temp_to_count(sc, sc->temp_throttle_val);
603 sc->temp_throttle_reset_cnt =
604 temp_to_count(sc, sc->temp_throttle_val - 50);
607 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set
608 * the throttle count, and begin making measurements.
610 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800);
611 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0,
612 (sc->temp_throttle_trigger_cnt <<
613 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) |
614 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE);
617 * XXX Note that the alarm-interrupt feature isn't working yet, so
618 * we'll use a callout handler to check at 10Hz. Make sure we have an
619 * initial temperature reading before starting up the callouts so we
620 * don't get a bogus reading of zero.
622 while (sc->temp_last_cnt == 0)
623 temp_update_count(sc);
624 sc->temp_throttle_delay = 100 * SBT_1MS;
625 callout_init(&sc->temp_throttle_callout, 0);
626 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
627 0, tempmon_throttle_check, sc, 0);
629 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
630 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0,
631 temp_sysctl_handler, "IK", "Current die temperature");
632 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
633 OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc,
634 0, temp_throttle_sysctl_handler, "IK",
635 "Throttle CPU when exceeding this temperature");
639 intr_setup(void *arg)
642 struct imx6_anatop_softc *sc;
646 sc->res[IRQRES] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
648 if (sc->res[IRQRES] != NULL) {
649 bus_setup_intr(sc->dev, sc->res[IRQRES],
650 INTR_TYPE_MISC | INTR_MPSAFE, tempmon_intr, NULL, sc,
653 device_printf(sc->dev, "Cannot allocate IRQ resource\n");
655 config_intrhook_disestablish(&sc->intr_setup_hook);
659 imx6_anatop_new_pass(device_t dev)
661 struct imx6_anatop_softc *sc;
662 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE;
665 * We attach during BUS_PASS_BUS (because some day we will be a
666 * simplebus that has regulator devices as children), but some of our
667 * init work cannot be done until BUS_PASS_CPU (we rely on other devices
668 * that attach on the CPU pass).
670 sc = device_get_softc(dev);
671 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) {
672 sc->cpu_init_done = true;
673 cpufreq_initialize(sc);
674 initialize_tempmon(sc);
676 device_printf(sc->dev, "CPU %uMHz @ %umV\n",
677 sc->cpu_curmhz, sc->cpu_curmv);
680 bus_generic_new_pass(dev);
684 imx6_anatop_detach(device_t dev)
687 /* This device can never detach. */
692 imx6_anatop_attach(device_t dev)
694 struct imx6_anatop_softc *sc;
697 sc = device_get_softc(dev);
700 /* Allocate bus_space resources. */
701 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
702 device_printf(dev, "Cannot allocate resources\n");
707 sc->intr_setup_hook.ich_func = intr_setup;
708 sc->intr_setup_hook.ich_arg = sc;
709 config_intrhook_establish(&sc->intr_setup_hook);
711 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
712 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
713 OID_AUTO, "cpu_voltage", CTLFLAG_RD,
714 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
719 * Other code seen on the net sets this SELFBIASOFF flag around the same
720 * time the temperature sensor is set up, although it's unclear how the
721 * two are related (if at all).
723 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
724 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
727 * Some day, when we're ready to deal with the actual anatop regulators
728 * that are described in fdt data as children of this "bus", this would
729 * be the place to invoke a simplebus helper routine to instantiate the
730 * children from the fdt data.
738 bus_release_resources(dev, imx6_anatop_spec, sc->res);
745 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
751 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
754 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);
755 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \
756 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
757 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
758 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);
759 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn);
760 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd);
766 imx6_anatop_probe(device_t dev)
769 if (!ofw_bus_status_okay(dev))
772 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0)
775 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power");
777 return (BUS_PROBE_DEFAULT);
781 imx6_get_cpu_clock(void)
783 uint32_t corediv, plldiv;
785 corediv = imx_ccm_get_cacrr();
786 plldiv = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
787 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
788 return (cpufreq_mhz_from_div(imx6_anatop_sc, corediv, plldiv));
791 static device_method_t imx6_anatop_methods[] = {
792 /* Device interface */
793 DEVMETHOD(device_probe, imx6_anatop_probe),
794 DEVMETHOD(device_attach, imx6_anatop_attach),
795 DEVMETHOD(device_detach, imx6_anatop_detach),
798 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass),
803 static driver_t imx6_anatop_driver = {
806 sizeof(struct imx6_anatop_softc)
809 static devclass_t imx6_anatop_devclass;
811 EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver,
812 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
813 EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver,
814 imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);