2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Clocks and power control driver for Freescale i.MX6 family of SoCs.
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
46 #include <machine/bus.h>
48 #include <arm/freescale/imx/imx6_anatopreg.h>
49 #include <arm/freescale/imx/imx6_anatopvar.h>
50 #include <arm/freescale/imx/imx6_ccmreg.h>
51 #include <arm/freescale/imx/imx_machdep.h>
52 #include <arm/freescale/imx/imx_ccmvar.h>
54 #ifndef CCGR_CLK_MODE_ALWAYS
55 #define CCGR_CLK_MODE_OFF 0
56 #define CCGR_CLK_MODE_RUNMODE 1
57 #define CCGR_CLK_MODE_ALWAYS 3
62 struct resource *mem_res;
65 static struct ccm_softc *ccm_sc;
67 static inline uint32_t
68 RD4(struct ccm_softc *sc, bus_size_t off)
71 return (bus_read_4(sc->mem_res, off));
75 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val)
78 bus_write_4(sc->mem_res, off, val);
82 * Until we have a fully functional ccm driver which implements the fdt_clock
83 * interface, use the age-old workaround of unconditionally enabling the clocks
84 * for devices we might need to use. The SoC defaults to most clocks enabled,
85 * but the rom boot code and u-boot disable a few of them. We turn on only
86 * what's needed to run the chip plus devices we have drivers for, and turn off
87 * devices we don't yet have drivers for. (Note that USB is not turned on here
88 * because that is one we do when the driver asks for it.)
91 ccm_init_gates(struct ccm_softc *sc)
95 /* ahpbdma, aipstz 1 & 2 buses */
96 reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;
97 WR4(sc, CCM_CCGR0, reg);
99 /* enet, epit, gpt, spi */
100 reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 |
101 CCGR1_ECSPI2 | CCGR1_ECSPI3 | CCGR1_ECSPI4 | CCGR1_ECSPI5;
102 WR4(sc, CCM_CCGR1, reg);
104 /* ipmux & ipsync (bridges), iomux, i2c */
105 reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |
106 CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 |
107 CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 |
109 WR4(sc, CCM_CCGR2, reg);
111 /* DDR memory controller */
112 reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |
113 CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13;
114 WR4(sc, CCM_CCGR3, reg);
116 /* pl301 bus crossbar */
117 reg = CCGR4_PL301_MX6QFAST1_S133 |
118 CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN;
119 WR4(sc, CCM_CCGR4, reg);
121 /* uarts, ssi, sdma */
122 reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |
123 CCGR5_UART | CCGR5_UART_SERIAL;
124 WR4(sc, CCM_CCGR5, reg);
126 /* usdhc 1-4, usboh3 */
127 reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |
128 CCGR6_USDHC3 | CCGR6_USDHC4;
129 WR4(sc, CCM_CCGR6, reg);
133 ccm_detach(device_t dev)
135 struct ccm_softc *sc;
137 sc = device_get_softc(dev);
139 if (sc->mem_res != NULL)
140 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
146 ccm_attach(device_t dev)
148 struct ccm_softc *sc;
152 sc = device_get_softc(dev);
155 /* Allocate bus_space resources. */
157 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
159 if (sc->mem_res == NULL) {
160 device_printf(dev, "Cannot allocate memory resources\n");
168 * Configure the Low Power Mode setting to leave the ARM core power on
169 * when a WFI instruction is executed. This lets the MPCore timers and
170 * GIC continue to run, which is helpful when the only thing that can
171 * wake you up is an MPCore Private Timer interrupt delivered via GIC.
173 * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be
174 * required when the LPM bits are set to LPM_RUN. But experimentally
175 * I've experienced a fairly rare lockup when not setting it. I was
176 * unable to prove conclusively that the lockup was related to power
177 * management or that this definitively fixes it. Revisit this.
179 reg = RD4(sc, CCM_CGPR);
180 reg |= CCM_CGPR_INT_MEM_CLK_LPM;
181 WR4(sc, CCM_CGPR, reg);
182 reg = RD4(sc, CCM_CLPCR);
183 reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;
184 WR4(sc, CCM_CLPCR, reg);
199 ccm_probe(device_t dev)
202 if (!ofw_bus_status_okay(dev))
205 if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0)
208 device_set_desc(dev, "Freescale i.MX6 Clock Control Module");
210 return (BUS_PROBE_DEFAULT);
214 imx_ccm_ssi_configure(device_t _ssidev)
216 struct ccm_softc *sc;
222 * Select PLL4 (Audio PLL) clock multiplexer as source.
223 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM).
226 reg = RD4(sc, CCM_CSCMR1);
227 reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);
228 reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);
229 reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);
230 reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);
231 reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);
232 reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);
233 WR4(sc, CCM_CSCMR1, reg);
236 * Ensure we have set hardware-default values
237 * for pre and post dividers.
241 reg = RD4(sc, CCM_CS1CDR);
243 reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);
244 reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);
245 reg |= (0x1 << SSI1_CLK_PODF_SHIFT);
246 reg |= (0x1 << SSI3_CLK_PODF_SHIFT);
248 reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);
249 reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);
250 reg |= (0x3 << SSI1_CLK_PRED_SHIFT);
251 reg |= (0x3 << SSI3_CLK_PRED_SHIFT);
252 WR4(sc, CCM_CS1CDR, reg);
255 reg = RD4(sc, CCM_CS2CDR);
257 reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);
258 reg |= (0x1 << SSI2_CLK_PODF_SHIFT);
260 reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);
261 reg |= (0x3 << SSI2_CLK_PRED_SHIFT);
262 WR4(sc, CCM_CS2CDR, reg);
266 imx_ccm_usb_enable(device_t _usbdev)
270 * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for
271 * shifting and masking here, just set the low-order two bits to ALWAYS.
273 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
277 imx_ccm_usbphy_enable(device_t _phydev)
281 * Right now it's not clear how to figure from fdt data which phy unit
282 * we're supposed to operate on. Until this is worked out, just enable
288 phy_num = 0; /* XXX */
298 device_printf(ccm_sc->dev, "Bad PHY number %u,\n",
303 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff,
304 IMX6_ANALOG_CCM_PLL_USB_ENABLE |
305 IMX6_ANALOG_CCM_PLL_USB_POWER |
306 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
308 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0,
309 IMX6_ANALOG_CCM_PLL_USB_ENABLE |
310 IMX6_ANALOG_CCM_PLL_USB_POWER |
311 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
313 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10,
314 IMX6_ANALOG_CCM_PLL_USB_ENABLE |
315 IMX6_ANALOG_CCM_PLL_USB_POWER |
316 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
321 imx6_ccm_sata_enable(void)
326 /* Un-gate the sata controller. */
327 WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
329 /* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */
330 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
331 v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN;
332 WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
334 for (timeout = 100000; timeout > 0; timeout--) {
335 if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) &
336 CCM_ANALOG_PLL_ENET_LOCK) {
344 /* Enable the PLL, and enable its 100mhz output. */
345 v |= CCM_ANALOG_PLL_ENET_ENABLE;
346 v &= ~CCM_ANALOG_PLL_ENET_BYPASS;
347 WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
349 v |= CCM_ANALOG_PLL_ENET_ENABLE_100M;
350 WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
356 imx_ccm_ecspi_hz(void)
370 imx_ccm_perclk_hz(void)
377 imx_ccm_sdhci_hz(void)
384 imx_ccm_uart_hz(void)
397 imx_ccm_ipu_enable(int ipu)
399 struct ccm_softc *sc;
403 reg = RD4(sc, CCM_CCGR3);
405 reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;
407 reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;
408 WR4(sc, CCM_CCGR3, reg);
412 imx_ccm_hdmi_enable(void)
414 struct ccm_softc *sc;
418 reg = RD4(sc, CCM_CCGR2);
419 reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;
420 WR4(sc, CCM_CCGR2, reg);
422 /* Set HDMI clock to 280MHz */
423 reg = RD4(sc, CCM_CHSCCDR);
424 reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
425 CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
426 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
427 reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
428 WR4(sc, CCM_CHSCCDR, reg);
429 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
430 WR4(sc, CCM_CHSCCDR, reg);
434 imx_ccm_get_cacrr(void)
437 return (RD4(ccm_sc, CCM_CACCR));
441 imx_ccm_set_cacrr(uint32_t divisor)
444 WR4(ccm_sc, CCM_CACCR, divisor);
447 static device_method_t ccm_methods[] = {
448 /* Device interface */
449 DEVMETHOD(device_probe, ccm_probe),
450 DEVMETHOD(device_attach, ccm_attach),
451 DEVMETHOD(device_detach, ccm_detach),
456 static driver_t ccm_driver = {
459 sizeof(struct ccm_softc)
462 static devclass_t ccm_devclass;
464 EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0,
465 BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);