sys/arm/freescale/imx/imx6_ccmreg.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #ifndef IMX6_CCMREG_H
  32 #define IMX6_CCMREG_H
  33
  34 #define CCM_CACCR                               0x010
  35 #define CCM_CBCDR                               0x014
  36 #define   CBCDR_MMDC_CH1_AXI_PODF_SHIFT           3
  37 #define   CBCDR_MMDC_CH1_AXI_PODF_MASK            (7 << 3)
  38 #define CCM_CSCMR1                              0x01C
  39 #define   SSI1_CLK_SEL_S                          10
  40 #define   SSI2_CLK_SEL_S                          12
  41 #define   SSI3_CLK_SEL_S                          14
  42 #define   SSI_CLK_SEL_M                           0x3
  43 #define   SSI_CLK_SEL_508_PFD                     0
  44 #define   SSI_CLK_SEL_454_PFD                     1
  45 #define   SSI_CLK_SEL_PLL4                        2
  46 #define CCM_CSCMR2                              0x020
  47 #define   CSCMR2_LDB_DI0_IPU_DIV_SHIFT            10
  48 #define CCM_CS1CDR                              0x028
  49 #define   SSI1_CLK_PODF_SHIFT                     0
  50 #define   SSI1_CLK_PRED_SHIFT                     6
  51 #define   SSI3_CLK_PODF_SHIFT                     16
  52 #define   SSI3_CLK_PRED_SHIFT                     22
  53 #define   SSI_CLK_PODF_MASK                       0x3f
  54 #define   SSI_CLK_PRED_MASK                       0x7
  55 #define CCM_CS2CDR                              0x02C
  56 #define   SSI2_CLK_PODF_SHIFT                     0
  57 #define   SSI2_CLK_PRED_SHIFT                     6
  58 #define   LDB_DI0_CLK_SEL_SHIFT                   9
  59 #define   LDB_DI0_CLK_SEL_MASK                    (3 << LDB_DI0_CLK_SEL_SHIFT)
  60 #define CCM_CHSCCDR                             0x034
  61 #define   CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK       (0x7 << 6)
  62 #define   CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT      6
  63 #define   CHSCCDR_IPU1_DI0_PODF_MASK              (0x7 << 3)
  64 #define   CHSCCDR_IPU1_DI0_PODF_SHIFT             3
  65 #define   CHSCCDR_IPU1_DI0_CLK_SEL_MASK           (0x7)
  66 #define   CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT          0
  67 #define   CHSCCDR_CLK_SEL_LDB_DI0                 3
  68 #define   CHSCCDR_PODF_DIVIDE_BY_3                2
  69 #define   CHSCCDR_IPU_PRE_CLK_540M_PFD            5
  70 #define CCM_CSCDR2                              0x038
  71 #define CCM_CLPCR                               0x054
  72 #define   CCM_CLPCR_LPM_MASK                      0x03
  73 #define   CCM_CLPCR_LPM_RUN                       0x00
  74 #define   CCM_CLPCR_LPM_WAIT                      0x01
  75 #define   CCM_CLPCR_LPM_STOP                      0x02
  76 #define CCM_CGPR                                0x064
  77 #define   CCM_CGPR_INT_MEM_CLK_LPM                (1 << 17)
  78 #define CCM_CCGR0                               0x068
  79 #define   CCGR0_AIPS_TZ1                          (0x3 << 0)
  80 #define   CCGR0_AIPS_TZ2                          (0x3 << 2)
  81 #define   CCGR0_ABPHDMA                           (0x3 << 4)
  82 #define CCM_CCGR1                               0x06C
  83 #define   CCGR1_ECSPI1                            (0x3 <<  0)
  84 #define   CCGR1_ECSPI2                            (0x3 <<  2)
  85 #define   CCGR1_ECSPI3                            (0x3 <<  4)
  86 #define   CCGR1_ECSPI4                            (0x3 <<  6)
  87 #define   CCGR1_ECSPI5                            (0x3 <<  8)
  88 #define   CCGR1_ENET                              (0x3 << 10)
  89 #define   CCGR1_EPIT1                             (0x3 << 12)
  90 #define   CCGR1_EPIT2                             (0x3 << 14)
  91 #define   CCGR1_ESAI                              (0x3 << 16)
  92 #define   CCGR1_GPT                               (0x3 << 20)
  93 #define   CCGR1_GPT_SERIAL                        (0x3 << 22)
  94 #define CCM_CCGR2                               0x070
  95 #define   CCGR2_HDMI_TX                           (0x3 << 0)
  96 #define   CCGR2_HDMI_TX_ISFR                      (0x3 << 4)
  97 #define   CCGR2_I2C1                              (0x3 << 6)
  98 #define   CCGR2_I2C2                              (0x3 << 8)
  99 #define   CCGR2_I2C3                              (0x3 << 10)
 100 #define   CCGR2_IIM                               (0x3 << 12)
 101 #define   CCGR2_IOMUX_IPT                         (0x3 << 14)
 102 #define   CCGR2_IPMUX1                            (0x3 << 16)
 103 #define   CCGR2_IPMUX2                            (0x3 << 18)
 104 #define   CCGR2_IPMUX3                            (0x3 << 20)
 105 #define   CCGR2_IPSYNC_IP2APB_TZASC1              (0x3 << 22)
 106 #define   CCGR2_IPSYNC_IP2APB_TZASC2              (0x3 << 24)
 107 #define   CCGR2_IPSYNC_VDOA                       (0x3 << 26)
 108 #define CCM_CCGR3                               0x074
 109 #define   CCGR3_IPU1_IPU                          (0x3 << 0)
 110 #define   CCGR3_IPU1_DI0                          (0x3 << 2)
 111 #define   CCGR3_IPU1_DI1                          (0x3 << 4)
 112 #define   CCGR3_IPU2_IPU                          (0x3 << 6)
 113 #define   CCGR3_IPU2_DI0                          (0x3 << 8)
 114 #define   CCGR3_IPU2_DI1                          (0x3 << 10)
 115 #define   CCGR3_LDB_DI0                           (0x3 << 12)
 116 #define   CCGR3_LDB_DI1                           (0x3 << 14)
 117 #define   CCGR3_MMDC_CORE_ACLK_FAST               (0x3 << 20)
 118 #define   CCGR3_CG11                              (0x3 << 22)
 119 #define   CCGR3_MMDC_CORE_IPG                     (0x3 << 24)
 120 #define   CCGR3_CG13                              (0x3 << 26)
 121 #define   CCGR3_OCRAM                             (0x3 << 28)
 122 #define CCM_CCGR4                               0x078
 123 #define   CCGR4_PL301_MX6QFAST1_S133              (0x3 << 8)
 124 #define   CCGR4_PL301_MX6QPER1_BCH                (0x3 << 12)
 125 #define   CCGR4_PL301_MX6QPER2_MAIN               (0x3 << 14)
 126 #define CCM_CCGR5                               0x07C
 127 #define   CCGR5_SATA                              (0x3 << 4)
 128 #define   CCGR5_SDMA                              (0x3 << 6)
 129 #define   CCGR5_SSI1                              (0x3 << 18)
 130 #define   CCGR5_SSI2                              (0x3 << 20)
 131 #define   CCGR5_SSI3                              (0x3 << 22)
 132 #define   CCGR5_UART                              (0x3 << 24)
 133 #define   CCGR5_UART_SERIAL                       (0x3 << 26)
 134 #define CCM_CCGR6                               0x080
 135 #define   CCGR6_USBOH3                            (0x3 << 0)
 136 #define   CCGR6_USDHC1                            (0x3 << 2)
 137 #define   CCGR6_USDHC2                            (0x3 << 4)
 138 #define   CCGR6_USDHC3                            (0x3 << 6)
 139 #define   CCGR6_USDHC4                            (0x3 << 8)
 140 #define CCM_CMEOR                               0x088
 141
 142 #define CCM_ANALOG_PLL_ENET                     0x000040e0
 143 #define   CCM_ANALOG_PLL_ENET_LOCK                (1u << 31)
 144 #define   CCM_ANALOG_PLL_ENET_ENABLE_100M         (1u << 20)  /* SATA */
 145 #define   CCM_ANALOG_PLL_ENET_BYPASS              (1u << 16)
 146 #define   CCM_ANALOG_PLL_ENET_ENABLE              (1u << 13)  /* Ether */
 147 #define   CCM_ANALOG_PLL_ENET_POWERDOWN           (1u << 12)
 148
 149 #endif