2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * Driver for imx6 Secure Non-Volatile Storage system, which really means "all
32 * the stuff that's powered by a battery when main power is off". This includes
33 * realtime clock, tamper monitor, and power-management functions. Currently
34 * this driver provides only realtime clock support.
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/clock.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <machine/bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
49 #define SNVS_LPCR 0x38 /* Control register */
50 #define LPCR_LPCALB_VAL_SHIFT 10 /* Calibration shift */
51 #define LPCR_LPCALB_VAL_MASK 0x1f /* Calibration mask */
52 #define LPCR_LPCALB_EN (1u << 8) /* Calibration enable */
53 #define LPCR_SRTC_ENV (1u << 0) /* RTC enabled/valid */
55 #define SNVS_LPSRTCMR 0x50 /* Counter MSB */
56 #define SNVS_LPSRTCLR 0x54 /* Counter LSB */
58 #define RTC_RESOLUTION_US (1000000 / 32768) /* 32khz clock */
61 * The RTC is a 47-bit counter clocked at 32KHz and organized as a 32.15
62 * fixed-point binary value. Shifting by SBT_LSB bits translates between
63 * counter and sbintime values.
67 #define SBT_LSB (SBT_BITS - RTC_BITS)
71 struct resource * memres;
75 static struct ofw_compat_data compat_data[] = {
76 {"fsl,sec-v4.0-mon-rtc-lp", true},
77 {"fsl,sec-v4.0-mon", true},
81 static inline uint32_t
82 RD4(struct snvs_softc *sc, bus_size_t offset)
85 return (bus_read_4(sc->memres, offset));
89 WR4(struct snvs_softc *sc, bus_size_t offset, uint32_t value)
92 bus_write_4(sc->memres, offset, value);
96 snvs_rtc_enable(struct snvs_softc *sc, bool enable)
101 sc->lpcr |= LPCR_SRTC_ENV;
103 sc->lpcr &= ~LPCR_SRTC_ENV;
104 WR4(sc, SNVS_LPCR, sc->lpcr);
106 /* Wait for the hardware to achieve the requested state. */
107 enbit = sc->lpcr & LPCR_SRTC_ENV;
108 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit)
113 snvs_gettime(device_t dev, struct timespec *ts)
115 struct snvs_softc *sc;
116 sbintime_t counter1, counter2;
118 sc = device_get_softc(dev);
120 /* If the clock is not enabled and valid, we can't help. */
121 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) {
126 * The counter is clocked asynchronously to cpu accesses; read and
127 * assemble the pieces of the counter until we get the same value twice.
128 * The counter is 47 bits, organized as a 32.15 binary fixed-point
129 * value. If we shift it up to the high order part of a 64-bit word it
130 * turns into an sbintime.
133 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
134 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
135 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
136 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
137 } while (counter1 != counter2);
139 *ts = sbttots(counter1);
141 clock_dbgprint_ts(sc->dev, CLOCK_DBG_READ, ts);
147 snvs_settime(device_t dev, struct timespec *ts)
149 struct snvs_softc *sc;
152 sc = device_get_softc(dev);
155 * The hardware format is the same as sbt (with fewer fractional bits),
156 * so first convert the time to sbt. It takes two clock cycles for the
157 * counter to start after setting the enable bit, so add two SBT_LSBs to
158 * what we're about to set.
162 snvs_rtc_enable(sc, false);
163 WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32)));
164 WR4(sc, SNVS_LPSRTCLR, (uint32_t)(sbt >> (SBT_LSB)));
165 snvs_rtc_enable(sc, true);
167 clock_dbgprint_ts(sc->dev, CLOCK_DBG_WRITE, ts);
173 snvs_probe(device_t dev)
176 if (!ofw_bus_status_okay(dev))
179 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
182 device_set_desc(dev, "i.MX6 SNVS RTC");
183 return (BUS_PROBE_DEFAULT);
187 snvs_attach(device_t dev)
189 struct snvs_softc *sc;
192 sc = device_get_softc(dev);
196 sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
198 if (sc->memres == NULL) {
199 device_printf(sc->dev, "could not allocate registers\n");
203 clock_register(sc->dev, RTC_RESOLUTION_US);
209 snvs_detach(device_t dev)
211 struct snvs_softc *sc;
213 sc = device_get_softc(dev);
214 clock_unregister(sc->dev);
215 bus_release_resource(sc->dev, SYS_RES_MEMORY, 0, sc->memres);
219 static device_method_t snvs_methods[] = {
220 DEVMETHOD(device_probe, snvs_probe),
221 DEVMETHOD(device_attach, snvs_attach),
222 DEVMETHOD(device_detach, snvs_detach),
224 /* clock_if methods */
225 DEVMETHOD(clock_gettime, snvs_gettime),
226 DEVMETHOD(clock_settime, snvs_settime),
231 static driver_t snvs_driver = {
234 sizeof(struct snvs_softc),
237 static devclass_t snvs_devclass;
239 DRIVER_MODULE(snvs, simplebus, snvs_driver, snvs_devclass, 0, 0);
240 SIMPLEBUS_PNP_INFO(compat_data);