2 * Copyright (c) 2012, 2013 The FreeBSD Foundation
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Freescale i.MX515 GPIO driver.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_platform.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
47 #include <sys/mutex.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
53 #include <machine/resource.h>
55 #include <dev/gpio/gpiobusvar.h>
56 #include <dev/ofw/openfirm.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
66 #define WRITE4(_sc, _r, _v) \
67 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
68 #define READ4(_sc, _r) \
69 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
70 #define SET4(_sc, _r, _m) \
71 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
72 #define CLEAR4(_sc, _r, _m) \
73 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
75 /* Registers definition for Freescale i.MX515 GPIO controller */
77 #define IMX_GPIO_DR_REG 0x000 /* Pin Data */
78 #define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */
79 #define IMX_GPIO_PSR_REG 0x008 /* Pad Status */
80 #define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */
81 #define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */
82 #define GPIO_ICR_COND_LOW 0
83 #define GPIO_ICR_COND_HIGH 1
84 #define GPIO_ICR_COND_RISE 2
85 #define GPIO_ICR_COND_FALL 3
86 #define GPIO_ICR_COND_MASK 0x3
87 #define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */
88 #define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */
89 #define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */
92 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
93 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \
94 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
96 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
103 struct intr_irqsrc gi_isrc;
109 struct imx51_gpio_softc {
113 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */
115 bus_space_tag_t sc_iot;
116 bus_space_handle_t sc_ioh;
118 struct gpio_pin gpio_pins[NGPIO];
120 struct gpio_irqsrc gpio_pic_irqsrc[NGPIO];
124 static struct ofw_compat_data compat_data[] = {
125 {"fsl,imx6q-gpio", 1},
126 {"fsl,imx53-gpio", 1},
127 {"fsl,imx51-gpio", 1},
131 static struct resource_spec imx_gpio_spec[] = {
132 { SYS_RES_MEMORY, 0, RF_ACTIVE },
133 { SYS_RES_IRQ, 0, RF_ACTIVE },
134 { SYS_RES_IRQ, 1, RF_ACTIVE },
137 #define FIRST_IRQRES 1
143 static void imx51_gpio_pin_configure(struct imx51_gpio_softc *,
144 struct gpio_pin *, uint32_t);
149 static int imx51_gpio_probe(device_t);
150 static int imx51_gpio_attach(device_t);
151 static int imx51_gpio_detach(device_t);
156 static device_t imx51_gpio_get_bus(device_t);
157 static int imx51_gpio_pin_max(device_t, int *);
158 static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
159 static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
160 static int imx51_gpio_pin_getname(device_t, uint32_t, char *);
161 static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t);
162 static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int);
163 static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *);
164 static int imx51_gpio_pin_toggle(device_t, uint32_t pin);
168 gpio_pic_map_fdt(struct imx51_gpio_softc *sc, struct intr_map_data_fdt *daf,
169 u_int *irqp, uint32_t *modep)
175 * From devicetree/bindings/gpio/fsl-imx-gpio.txt:
176 * #interrupt-cells: 2. The first cell is the GPIO number. The second
177 * cell bits[3:0] is used to specify trigger type and level flags:
178 * 1 = low-to-high edge triggered.
179 * 2 = high-to-low edge triggered.
180 * 4 = active high level-sensitive.
181 * 8 = active low level-sensitive.
182 * We can do any single one of these modes, and also edge low+high
183 * (i.e., trigger on both edges); other combinations are not supported.
186 if (daf->ncells != 2) {
187 device_printf(sc->dev, "Invalid #interrupt-cells\n");
192 if (irq >= sc->gpio_npins) {
193 device_printf(sc->dev, "Invalid interrupt number %u\n", irq);
196 switch (daf->cells[1]) {
198 mode = GPIO_INTR_EDGE_RISING;
201 mode = GPIO_INTR_EDGE_FALLING;
204 mode = GPIO_INTR_EDGE_BOTH;
207 mode = GPIO_INTR_LEVEL_HIGH;
210 mode = GPIO_INTR_LEVEL_LOW;
213 device_printf(sc->dev, "Unsupported interrupt mode 0x%2x\n",
224 gpio_pic_map_gpio(struct imx51_gpio_softc *sc, struct intr_map_data_gpio *dag,
225 u_int *irqp, uint32_t *modep)
229 irq = dag->gpio_pin_num;
230 if (irq >= sc->gpio_npins) {
231 device_printf(sc->dev, "Invalid interrupt number %u\n", irq);
235 switch (dag->gpio_intr_mode) {
236 case GPIO_INTR_LEVEL_LOW:
237 case GPIO_INTR_LEVEL_HIGH:
238 case GPIO_INTR_EDGE_RISING:
239 case GPIO_INTR_EDGE_FALLING:
240 case GPIO_INTR_EDGE_BOTH:
243 device_printf(sc->dev, "Unsupported interrupt mode 0x%8x\n",
244 dag->gpio_intr_mode);
250 *modep = dag->gpio_intr_mode;
255 gpio_pic_map(struct imx51_gpio_softc *sc, struct intr_map_data *data,
256 u_int *irqp, uint32_t *modep)
259 switch (data->type) {
260 case INTR_MAP_DATA_FDT:
261 return (gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data,
263 case INTR_MAP_DATA_GPIO:
264 return (gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data,
272 gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
273 struct intr_irqsrc **isrcp)
277 struct imx51_gpio_softc *sc;
279 sc = device_get_softc(dev);
280 error = gpio_pic_map(sc, data, &irq, NULL);
282 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc;
287 gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
288 struct resource *res, struct intr_map_data *data)
290 struct imx51_gpio_softc *sc;
291 struct gpio_irqsrc *gi;
293 sc = device_get_softc(dev);
294 if (isrc->isrc_handlers == 0) {
295 gi = (struct gpio_irqsrc *)isrc;
296 gi->gi_mode = GPIO_INTR_CONFORM;
298 // XXX Not sure this is necessary
299 mtx_lock_spin(&sc->sc_mtx);
300 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq));
301 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq));
302 mtx_unlock_spin(&sc->sc_mtx);
308 gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
309 struct resource *res, struct intr_map_data *data)
311 struct imx51_gpio_softc *sc;
312 struct gpio_irqsrc *gi;
314 u_int icfg, irq, reg, shift, wrk;
320 sc = device_get_softc(dev);
321 gi = (struct gpio_irqsrc *)isrc;
323 /* Get config for interrupt. */
324 error = gpio_pic_map(sc, data, &irq, &mode);
327 if (gi->gi_irq != irq)
330 /* Compare config if this is not first setup. */
331 if (isrc->isrc_handlers != 0)
332 return (gi->gi_mode == mode ? 0 : EINVAL);
336 * To interrupt on both edges we have to use the EDGE register. The
337 * manual says it only exists for backwards compatibilty with older imx
338 * chips, but it's also the only way to configure interrupting on both
339 * edges. If the EDGE bit is on, the corresponding ICRn bit is ignored.
341 mtx_lock_spin(&sc->sc_mtx);
342 if (mode == GPIO_INTR_EDGE_BOTH) {
343 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq));
345 CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq));
348 /* silence warnings; default can't actually happen. */
350 case GPIO_INTR_LEVEL_LOW:
351 icfg = GPIO_ICR_COND_LOW;
353 case GPIO_INTR_LEVEL_HIGH:
354 icfg = GPIO_ICR_COND_HIGH;
356 case GPIO_INTR_EDGE_RISING:
357 icfg = GPIO_ICR_COND_RISE;
359 case GPIO_INTR_EDGE_FALLING:
360 icfg = GPIO_ICR_COND_FALL;
364 reg = IMX_GPIO_ICR1_REG;
367 reg = IMX_GPIO_ICR2_REG;
368 shift = 2 * (irq - 16);
370 wrk = READ4(sc, reg);
371 wrk &= ~(GPIO_ICR_COND_MASK << shift);
372 wrk |= icfg << shift;
373 WRITE4(sc, reg, wrk);
375 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq));
376 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq));
377 mtx_unlock_spin(&sc->sc_mtx);
386 gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
388 struct imx51_gpio_softc *sc;
391 sc = device_get_softc(dev);
392 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
394 mtx_lock_spin(&sc->sc_mtx);
395 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq));
396 mtx_unlock_spin(&sc->sc_mtx);
400 * this is unmask_intr
403 gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
405 struct imx51_gpio_softc *sc;
408 sc = device_get_softc(dev);
409 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
411 mtx_lock_spin(&sc->sc_mtx);
412 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq));
413 mtx_unlock_spin(&sc->sc_mtx);
417 gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
419 struct imx51_gpio_softc *sc;
422 sc = device_get_softc(dev);
423 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
425 arm_irq_memory_barrier(0);
426 /* EOI. W1C reg so no r-m-w, no locking needed. */
427 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
431 gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
433 struct imx51_gpio_softc *sc;
436 sc = device_get_softc(dev);
437 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
439 arm_irq_memory_barrier(0);
440 /* EOI. W1C reg so no r-m-w, no locking needed. */
441 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
442 gpio_pic_enable_intr(dev, isrc);
446 gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
448 gpio_pic_disable_intr(dev, isrc);
452 gpio_pic_filter(void *arg)
454 struct imx51_gpio_softc *sc;
455 struct intr_irqsrc *isrc;
456 uint32_t i, interrupts;
459 mtx_lock_spin(&sc->sc_mtx);
460 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG);
461 mtx_unlock_spin(&sc->sc_mtx);
463 for (i = 0; interrupts != 0; i++, interrupts >>= 1) {
464 if ((interrupts & 0x1) == 0)
466 isrc = &sc->gpio_pic_irqsrc[i].gi_isrc;
467 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
468 gpio_pic_disable_intr(sc->dev, isrc);
469 gpio_pic_post_filter(sc->dev, isrc);
470 device_printf(sc->dev, "Stray irq %u disabled\n", i);
474 return (FILTER_HANDLED);
478 * Initialize our isrcs and register them with intrng.
481 gpio_pic_register_isrcs(struct imx51_gpio_softc *sc)
487 name = device_get_nameunit(sc->dev);
488 for (irq = 0; irq < NGPIO; irq++) {
489 sc->gpio_pic_irqsrc[irq].gi_irq = irq;
490 sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM;
492 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc,
493 sc->dev, 0, "%s,%u", name, irq);
495 /* XXX call intr_isrc_deregister() */
496 device_printf(sc->dev, "%s failed", __func__);
508 imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin,
513 mtx_lock_spin(&sc->sc_mtx);
516 * Manage input/output; other flags not supported yet (maybe not ever,
517 * since we have no connection to the pad config registers from here).
519 * When setting a pin to output, honor the PRESET_[LOW,HIGH] flags if
520 * present. Otherwise, for glitchless transistions on pins with pulls,
521 * read the current state of the pad and preset the DR register to drive
522 * the current value onto the pin before enabling the pin for output.
524 * Note that changes to pin->gp_flags must be acccumulated in newflags
525 * and stored with a single writeback to gp_flags at the end, to enable
526 * unlocked reads of that value elsewhere. This is only about unlocked
527 * access to gp_flags from elsewhere; we still use locking in this
528 * function to protect r-m-w access to the hardware registers.
530 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
531 newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
532 if (flags & GPIO_PIN_OUTPUT) {
533 if (flags & GPIO_PIN_PRESET_LOW) {
535 } else if (flags & GPIO_PIN_PRESET_HIGH) {
538 if (flags & GPIO_PIN_OPENDRAIN)
539 pad = READ4(sc, IMX_GPIO_PSR_REG);
541 pad = READ4(sc, IMX_GPIO_DR_REG);
542 pad = (pad >> pin->gp_pin) & 1;
544 newflags |= GPIO_PIN_OUTPUT;
545 SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin));
546 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin));
548 newflags |= GPIO_PIN_INPUT;
549 CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin));
551 pin->gp_flags = newflags;
554 mtx_unlock_spin(&sc->sc_mtx);
558 imx51_gpio_get_bus(device_t dev)
560 struct imx51_gpio_softc *sc;
562 sc = device_get_softc(dev);
564 return (sc->sc_busdev);
568 imx51_gpio_pin_max(device_t dev, int *maxpin)
570 struct imx51_gpio_softc *sc;
572 sc = device_get_softc(dev);
573 *maxpin = sc->gpio_npins - 1;
579 imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
581 struct imx51_gpio_softc *sc;
583 sc = device_get_softc(dev);
585 if (pin >= sc->gpio_npins)
588 *caps = sc->gpio_pins[pin].gp_caps;
594 imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
596 struct imx51_gpio_softc *sc;
598 sc = device_get_softc(dev);
600 if (pin >= sc->gpio_npins)
603 *flags = sc->gpio_pins[pin].gp_flags;
609 imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
611 struct imx51_gpio_softc *sc;
613 sc = device_get_softc(dev);
614 if (pin >= sc->gpio_npins)
617 mtx_lock_spin(&sc->sc_mtx);
618 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
619 mtx_unlock_spin(&sc->sc_mtx);
625 imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
627 struct imx51_gpio_softc *sc;
629 sc = device_get_softc(dev);
631 if (pin >= sc->gpio_npins)
634 imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags);
640 imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
642 struct imx51_gpio_softc *sc;
644 sc = device_get_softc(dev);
646 if (pin >= sc->gpio_npins)
649 mtx_lock_spin(&sc->sc_mtx);
651 SET4(sc, IMX_GPIO_DR_REG, (1U << pin));
653 CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin));
654 mtx_unlock_spin(&sc->sc_mtx);
660 imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
662 struct imx51_gpio_softc *sc;
664 sc = device_get_softc(dev);
666 if (pin >= sc->gpio_npins)
670 * Normally a pin set for output can be read by reading the DR reg which
671 * indicates what value is being driven to that pin. The exception is
672 * pins configured for open-drain mode, in which case we have to read
673 * the pad status register in case the pin is being driven externally.
674 * Doing so requires that the SION bit be configured in pinmux, which
675 * isn't the case for most normal gpio pins, so only try to read via PSR
676 * if the OPENDRAIN flag is set, and it's the user's job to correctly
677 * configure SION along with open-drain output mode for those pins.
679 if (sc->gpio_pins[pin].gp_flags & GPIO_PIN_OPENDRAIN)
680 *val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1;
682 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1;
688 imx51_gpio_pin_toggle(device_t dev, uint32_t pin)
690 struct imx51_gpio_softc *sc;
692 sc = device_get_softc(dev);
694 if (pin >= sc->gpio_npins)
697 mtx_lock_spin(&sc->sc_mtx);
698 WRITE4(sc, IMX_GPIO_DR_REG,
699 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin)));
700 mtx_unlock_spin(&sc->sc_mtx);
706 imx51_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
707 uint32_t change_pins, uint32_t *orig_pins)
709 struct imx51_gpio_softc *sc;
714 sc = device_get_softc(dev);
716 if (orig_pins != NULL)
717 *orig_pins = READ4(sc, IMX_GPIO_DR_REG);
719 if ((clear_pins | change_pins) != 0) {
720 mtx_lock_spin(&sc->sc_mtx);
721 WRITE4(sc, IMX_GPIO_DR_REG,
722 (READ4(sc, IMX_GPIO_DR_REG) & ~clear_pins) ^ change_pins);
723 mtx_unlock_spin(&sc->sc_mtx);
730 imx51_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
733 struct imx51_gpio_softc *sc;
735 uint32_t bit, drclr, drset, flags, oeclr, oeset, pads;
737 sc = device_get_softc(dev);
739 if (first_pin != 0 || num_pins > sc->gpio_npins)
742 drclr = drset = oeclr = oeset = 0;
743 pads = READ4(sc, IMX_GPIO_DR_REG);
745 for (i = 0; i < num_pins; ++i) {
747 flags = pin_flags[i];
748 if (flags & GPIO_PIN_INPUT) {
750 } else if (flags & GPIO_PIN_OUTPUT) {
752 if (flags & GPIO_PIN_PRESET_LOW)
754 else if (flags & GPIO_PIN_PRESET_HIGH)
756 else /* Drive whatever it's now pulled to. */
761 mtx_lock_spin(&sc->sc_mtx);
762 WRITE4(sc, IMX_GPIO_DR_REG,
763 (READ4(sc, IMX_GPIO_DR_REG) & ~drclr) | drset);
764 WRITE4(sc, IMX_GPIO_OE_REG,
765 (READ4(sc, IMX_GPIO_OE_REG) & ~oeclr) | oeset);
766 mtx_unlock_spin(&sc->sc_mtx);
772 imx51_gpio_probe(device_t dev)
775 if (!ofw_bus_status_okay(dev))
778 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
779 device_set_desc(dev, "Freescale i.MX GPIO Controller");
780 return (BUS_PROBE_DEFAULT);
787 imx51_gpio_attach(device_t dev)
789 struct imx51_gpio_softc *sc;
792 sc = device_get_softc(dev);
794 sc->gpio_npins = NGPIO;
796 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN);
798 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) {
799 device_printf(dev, "could not allocate resources\n");
800 bus_release_resources(dev, imx_gpio_spec, sc->sc_res);
801 mtx_destroy(&sc->sc_mtx);
805 sc->sc_iot = rman_get_bustag(sc->sc_res[0]);
806 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]);
808 * Mask off all interrupts in hardware, then set up interrupt handling.
810 WRITE4(sc, IMX_GPIO_IMR_REG, 0);
811 for (irq = 0; irq < 2; irq++) {
813 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK,
814 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) {
816 "WARNING: unable to register interrupt handler\n");
817 imx51_gpio_detach(dev);
823 unit = device_get_unit(dev);
824 for (i = 0; i < sc->gpio_npins; i++) {
825 sc->gpio_pins[i].gp_pin = i;
826 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
827 sc->gpio_pins[i].gp_flags =
828 (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT :
830 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
831 "GPIO%d_IO%02d", unit + 1, i);
835 gpio_pic_register_isrcs(sc);
836 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
838 sc->sc_busdev = gpiobus_attach_bus(dev);
840 if (sc->sc_busdev == NULL) {
841 imx51_gpio_detach(dev);
849 imx51_gpio_detach(device_t dev)
852 struct imx51_gpio_softc *sc;
854 sc = device_get_softc(dev);
856 gpiobus_detach_bus(dev);
857 for (irq = 0; irq < NUM_IRQRES; irq++) {
858 if (sc->gpio_ih[irq])
859 bus_teardown_intr(dev, sc->sc_res[irq + FIRST_IRQRES],
862 bus_release_resources(dev, imx_gpio_spec, sc->sc_res);
863 mtx_destroy(&sc->sc_mtx);
869 imx51_gpio_get_node(device_t bus, device_t dev)
872 * Share controller node with gpiobus device
874 return ofw_bus_get_node(bus);
877 static device_method_t imx51_gpio_methods[] = {
878 DEVMETHOD(device_probe, imx51_gpio_probe),
879 DEVMETHOD(device_attach, imx51_gpio_attach),
880 DEVMETHOD(device_detach, imx51_gpio_detach),
883 /* Interrupt controller interface */
884 DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr),
885 DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr),
886 DEVMETHOD(pic_map_intr, gpio_pic_map_intr),
887 DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr),
888 DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr),
889 DEVMETHOD(pic_post_filter, gpio_pic_post_filter),
890 DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread),
891 DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread),
895 DEVMETHOD(ofw_bus_get_node, imx51_gpio_get_node),
898 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus),
899 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max),
900 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname),
901 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags),
902 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps),
903 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags),
904 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get),
905 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set),
906 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle),
907 DEVMETHOD(gpio_pin_access_32, imx51_gpio_pin_access_32),
908 DEVMETHOD(gpio_pin_config_32, imx51_gpio_pin_config_32),
912 static driver_t imx51_gpio_driver = {
915 sizeof(struct imx51_gpio_softc),
917 static devclass_t imx51_gpio_devclass;
919 EARLY_DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver,
920 imx51_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);