2 * Copyright (c) 2012, 2013 The FreeBSD Foundation
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Freescale i.MX515 GPIO driver.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
45 #include <sys/mutex.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
58 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
59 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
60 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \
61 device_get_nameunit(_sc->sc_dev), "imx_gpio", MTX_DEF)
62 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
63 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
64 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
66 #define WRITE4(_sc, _r, _v) \
67 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
68 #define READ4(_sc, _r) \
69 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
70 #define SET4(_sc, _r, _m) \
71 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
72 #define CLEAR4(_sc, _r, _m) \
73 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
75 /* Registers definition for Freescale i.MX515 GPIO controller */
77 #define IMX_GPIO_DR_REG 0x000 /* Pin Data */
78 #define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */
79 #define IMX_GPIO_PSR_REG 0x008 /* Pad Status */
80 #define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */
81 #define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */
82 #define GPIO_ICR_COND_LOW 0
83 #define GPIO_ICR_COND_HIGH 1
84 #define GPIO_ICR_COND_RISE 2
85 #define GPIO_ICR_COND_FALL 3
86 #define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */
87 #define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */
88 #define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */
90 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
93 struct imx51_gpio_softc {
96 struct resource *sc_res[11]; /* 1 x mem, 2 x IRQ, 8 x IRQ */
97 void *gpio_ih[11]; /* 1 ptr is not a big waste */
98 int sc_l_irq; /* Last irq resource */
99 bus_space_tag_t sc_iot;
100 bus_space_handle_t sc_ioh;
102 struct gpio_pin gpio_pins[NGPIO];
105 static struct ofw_compat_data compat_data[] = {
106 {"fsl,imx6q-gpio", 1},
107 {"fsl,imx53-gpio", 1},
108 {"fsl,imx51-gpio", 1},
112 static struct resource_spec imx_gpio_spec[] = {
113 { SYS_RES_MEMORY, 0, RF_ACTIVE },
114 { SYS_RES_IRQ, 0, RF_ACTIVE },
115 { SYS_RES_IRQ, 1, RF_ACTIVE },
119 static struct resource_spec imx_gpio0irq_spec[] = {
120 { SYS_RES_IRQ, 2, RF_ACTIVE },
121 { SYS_RES_IRQ, 3, RF_ACTIVE },
122 { SYS_RES_IRQ, 4, RF_ACTIVE },
123 { SYS_RES_IRQ, 5, RF_ACTIVE },
124 { SYS_RES_IRQ, 6, RF_ACTIVE },
125 { SYS_RES_IRQ, 7, RF_ACTIVE },
126 { SYS_RES_IRQ, 8, RF_ACTIVE },
127 { SYS_RES_IRQ, 9, RF_ACTIVE },
134 static void imx51_gpio_pin_configure(struct imx51_gpio_softc *,
135 struct gpio_pin *, uint32_t);
140 static int imx51_gpio_probe(device_t);
141 static int imx51_gpio_attach(device_t);
142 static int imx51_gpio_detach(device_t);
143 static int imx51_gpio_intr(void *);
148 static int imx51_gpio_pin_max(device_t, int *);
149 static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
150 static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
151 static int imx51_gpio_pin_getname(device_t, uint32_t, char *);
152 static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t);
153 static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int);
154 static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *);
155 static int imx51_gpio_pin_toggle(device_t, uint32_t pin);
158 imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin,
165 * Manage input/output
167 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
168 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
169 if (flags & GPIO_PIN_OUTPUT) {
170 pin->gp_flags |= GPIO_PIN_OUTPUT;
171 SET4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin));
174 pin->gp_flags |= GPIO_PIN_INPUT;
175 CLEAR4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin));
183 imx51_gpio_pin_max(device_t dev, int *maxpin)
191 imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
193 struct imx51_gpio_softc *sc;
196 sc = device_get_softc(dev);
197 for (i = 0; i < sc->gpio_npins; i++) {
198 if (sc->gpio_pins[i].gp_pin == pin)
202 if (i >= sc->gpio_npins)
206 *caps = sc->gpio_pins[i].gp_caps;
213 imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
215 struct imx51_gpio_softc *sc;
218 sc = device_get_softc(dev);
219 for (i = 0; i < sc->gpio_npins; i++) {
220 if (sc->gpio_pins[i].gp_pin == pin)
224 if (i >= sc->gpio_npins)
228 *flags = sc->gpio_pins[i].gp_flags;
235 imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
237 struct imx51_gpio_softc *sc;
240 sc = device_get_softc(dev);
241 for (i = 0; i < sc->gpio_npins; i++) {
242 if (sc->gpio_pins[i].gp_pin == pin)
246 if (i >= sc->gpio_npins)
250 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
257 imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
259 struct imx51_gpio_softc *sc;
262 sc = device_get_softc(dev);
263 for (i = 0; i < sc->gpio_npins; i++) {
264 if (sc->gpio_pins[i].gp_pin == pin)
268 if (i >= sc->gpio_npins)
271 /* Check for unwanted flags. */
272 if ((flags & sc->gpio_pins[i].gp_caps) != flags)
275 /* Can't mix input/output together */
276 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
277 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
280 imx51_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
287 imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
289 struct imx51_gpio_softc *sc;
292 sc = device_get_softc(dev);
293 for (i = 0; i < sc->gpio_npins; i++) {
294 if (sc->gpio_pins[i].gp_pin == pin)
298 if (i >= sc->gpio_npins)
303 SET4(sc, IMX_GPIO_DR_REG, (1 << i));
305 CLEAR4(sc, IMX_GPIO_DR_REG, (1 << i));
312 imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
314 struct imx51_gpio_softc *sc;
317 sc = device_get_softc(dev);
318 for (i = 0; i < sc->gpio_npins; i++) {
319 if (sc->gpio_pins[i].gp_pin == pin)
323 if (i >= sc->gpio_npins)
327 *val = (READ4(sc, IMX_GPIO_DR_REG) >> i) & 1;
334 imx51_gpio_pin_toggle(device_t dev, uint32_t pin)
336 struct imx51_gpio_softc *sc;
339 sc = device_get_softc(dev);
340 for (i = 0; i < sc->gpio_npins; i++) {
341 if (sc->gpio_pins[i].gp_pin == pin)
345 if (i >= sc->gpio_npins)
349 WRITE4(sc, IMX_GPIO_DR_REG,
350 (READ4(sc, IMX_GPIO_DR_REG) ^ (1 << i)));
357 imx51_gpio_intr(void *arg)
359 struct imx51_gpio_softc *sc;
360 uint32_t input, value;
363 input = READ4(sc, IMX_GPIO_ISR_REG);
364 value = input & READ4(sc, IMX_GPIO_IMR_REG);
365 WRITE4(sc, IMX_GPIO_ISR_REG, input);
370 /* TODO: interrupt handling */
373 return (FILTER_HANDLED);
377 imx51_gpio_probe(device_t dev)
380 if (!ofw_bus_status_okay(dev))
383 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
384 device_set_desc(dev, "Freescale i.MX GPIO Controller");
385 return (BUS_PROBE_DEFAULT);
392 imx51_gpio_attach(device_t dev)
394 struct imx51_gpio_softc *sc;
397 sc = device_get_softc(dev);
398 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
400 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) {
401 device_printf(dev, "could not allocate resources\n");
406 sc->gpio_npins = NGPIO;
408 sc->sc_iot = rman_get_bustag(sc->sc_res[0]);
409 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]);
411 if (bus_alloc_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]) == 0) {
413 * First GPIO unit able to serve +8 interrupts for 8 first
419 for (irq = 1; irq <= sc->sc_l_irq; irq ++) {
420 if ((bus_setup_intr(dev, sc->sc_res[irq], INTR_TYPE_MISC,
421 imx51_gpio_intr, NULL, sc, &sc->gpio_ih[irq]))) {
423 "WARNING: unable to register interrupt handler\n");
428 for (i = 0; i < sc->gpio_npins; i++) {
429 sc->gpio_pins[i].gp_pin = i;
430 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
431 sc->gpio_pins[i].gp_flags =
432 (READ4(sc, IMX_GPIO_OE_REG) & (1 << i)) ? GPIO_PIN_OUTPUT:
434 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
435 "imx_gpio%d.%d", device_get_unit(dev), i);
438 device_add_child(dev, "gpioc", device_get_unit(dev));
439 device_add_child(dev, "gpiobus", device_get_unit(dev));
441 return (bus_generic_attach(dev));
445 imx51_gpio_detach(device_t dev)
447 struct imx51_gpio_softc *sc;
449 sc = device_get_softc(dev);
451 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
453 bus_generic_detach(dev);
456 bus_release_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]);
459 bus_release_resources(dev, imx_gpio_spec, sc->sc_res);
461 mtx_destroy(&sc->sc_mtx);
466 static device_method_t imx51_gpio_methods[] = {
467 DEVMETHOD(device_probe, imx51_gpio_probe),
468 DEVMETHOD(device_attach, imx51_gpio_attach),
469 DEVMETHOD(device_detach, imx51_gpio_detach),
472 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max),
473 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname),
474 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags),
475 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps),
476 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags),
477 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get),
478 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set),
479 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle),
483 static driver_t imx51_gpio_driver = {
486 sizeof(struct imx51_gpio_softc),
488 static devclass_t imx51_gpio_devclass;
490 DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass,