2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
3 * Copyright (c) 2012, 2013 The FreeBSD Foundation
4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org>
7 * Portions of this software were developed by Oleksandr Rybalko
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * I2C driver for Freescale i.MX hardware.
35 * Note that the hardware is capable of running as both a master and a slave.
36 * This driver currently implements only master-mode operations.
38 * This driver supports multi-master i2c buses, by detecting bus arbitration
39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of
40 * retries if some other master jumps onto the bus and interrupts one of our
41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller
42 * must handle retries in a way that makes sense for the slave being addressed.
45 #include <sys/cdefs.h>
46 __FBSDID("$FreeBSD$");
48 #include <sys/param.h>
49 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/limits.h>
54 #include <sys/module.h>
55 #include <sys/resource.h>
56 #include <sys/sysctl.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
62 #include <arm/freescale/imx/imx_ccmvar.h>
64 #include <dev/iicbus/iiconf.h>
65 #include <dev/iicbus/iicbus.h>
66 #include <dev/iicbus/iic_recover_bus.h>
67 #include "iicbus_if.h"
69 #include <dev/ofw/openfirm.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
73 #include <dev/fdt/fdt_pinctrl.h>
74 #include <dev/gpio/gpiobusvar.h>
76 #define I2C_ADDR_REG 0x00 /* I2C slave address register */
77 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */
78 #define I2C_CONTROL_REG 0x08 /* I2C control register */
79 #define I2C_STATUS_REG 0x0C /* I2C status register */
80 #define I2C_DATA_REG 0x10 /* I2C data register */
81 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */
83 #define I2CCR_MEN (1 << 7) /* Module enable */
84 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */
85 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */
86 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */
87 #define I2CCR_RSTA (1 << 2) /* Repeated START */
89 #define I2CSR_MCF (1 << 7) /* Data transfer */
90 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */
91 #define I2CSR_MBB (1 << 5) /* Bus busy */
92 #define I2CSR_MAL (1 << 4) /* Arbitration lost */
93 #define I2CSR_SRW (1 << 2) /* Slave read/write */
94 #define I2CSR_MIF (1 << 1) /* Module interrupt */
95 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */
97 #define I2C_BAUD_RATE_FAST 0x31
98 #define I2C_BAUD_RATE_DEF 0x3F
99 #define I2C_DFSSR_DIV 0x10
102 * A table of available divisors and the associated coded values to put in the
103 * FDR register to achieve that divisor.. There is no algorithmic relationship I
104 * can see between divisors and the codes that go into the register. The table
105 * begins and ends with entries that handle insane configuration values.
111 static struct clkdiv clkdiv_table[] = {
112 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 },
113 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 },
114 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 },
115 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a },
116 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d },
117 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c },
118 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f },
119 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 },
120 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 },
121 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 },
122 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d },
123 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c },
124 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f}
127 static struct ofw_compat_data compat_data[] = {
128 {"fsl,imx6q-i2c", 1},
136 struct resource *res;
138 sbintime_t byte_time_sbt;
140 gpio_pin_t rb_sclpin;
141 gpio_pin_t rb_sdapin;
146 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \
147 if ((lvl) <= (sc)->debug) \
148 device_printf((sc)->dev, fmt, ##args)
150 #define DEBUGF(sc, lvl, fmt, args...) \
151 if ((lvl) <= (sc)->debug) \
154 static phandle_t i2c_get_node(device_t, device_t);
155 static int i2c_probe(device_t);
156 static int i2c_attach(device_t);
157 static int i2c_detach(device_t);
159 static int i2c_repeated_start(device_t, u_char, int);
160 static int i2c_start(device_t, u_char, int);
161 static int i2c_stop(device_t);
162 static int i2c_reset(device_t, u_char, u_char, u_char *);
163 static int i2c_read(device_t, char *, int, int *, int, int);
164 static int i2c_write(device_t, const char *, int, int *, int);
166 static device_method_t i2c_methods[] = {
167 DEVMETHOD(device_probe, i2c_probe),
168 DEVMETHOD(device_attach, i2c_attach),
169 DEVMETHOD(device_detach, i2c_detach),
172 DEVMETHOD(ofw_bus_get_node, i2c_get_node),
174 DEVMETHOD(iicbus_callback, iicbus_null_callback),
175 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
176 DEVMETHOD(iicbus_start, i2c_start),
177 DEVMETHOD(iicbus_stop, i2c_stop),
178 DEVMETHOD(iicbus_reset, i2c_reset),
179 DEVMETHOD(iicbus_read, i2c_read),
180 DEVMETHOD(iicbus_write, i2c_write),
181 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
186 static driver_t i2c_driver = {
189 sizeof(struct i2c_softc),
191 static devclass_t i2c_devclass;
193 DRIVER_MODULE(imx_i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
194 DRIVER_MODULE(ofw_iicbus, imx_i2c, ofw_iicbus_driver, ofw_iicbus_devclass, 0, 0);
195 MODULE_DEPEND(imx_i2c, iicbus, 1, 1, 1);
196 MODULE_DEPEND(imx_i2c, ofw_iicbus, 1, 1, 1);
199 i2c_get_node(device_t bus, device_t dev)
202 * Share controller node with iicbus device
204 return ofw_bus_get_node(bus);
208 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val)
211 bus_write_1(sc->res, off, val);
214 static __inline uint8_t
215 i2c_read_reg(struct i2c_softc *sc, bus_size_t off)
218 return (bus_read_1(sc->res, off));
222 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask)
226 status = i2c_read_reg(sc, off);
228 i2c_write_reg(sc, off, status);
231 /* Wait for bus to become busy or not-busy. */
233 wait_for_busbusy(struct i2c_softc *sc, int wantbusy)
239 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB;
240 if ((srb && wantbusy) || (!srb && !wantbusy))
244 return (IIC_ETIMEOUT);
247 /* Wait for transfer to complete, optionally check RXAK. */
249 wait_for_xfer(struct i2c_softc *sc, int checkack)
254 * Sleep for about the time it takes to transfer a byte (with precision
255 * set to tolerate 5% oversleep). We calculate the approximate byte
256 * transfer time when we set the bus speed divisor. Slaves are allowed
257 * to do clock-stretching so the actual transfer time can be larger, but
258 * this gets the bulk of the waiting out of the way without tying up the
259 * processor the whole time.
261 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0);
265 sr = i2c_read_reg(sc, I2C_STATUS_REG);
266 if (sr & I2CSR_MIF) {
268 return (IIC_EBUSERR);
269 else if (checkack && (sr & I2CSR_RXAK))
276 return (IIC_ETIMEOUT);
280 * Implement the error handling shown in the state diagram of the imx6 reference
281 * manual. If there was an error, then:
282 * - Clear master mode (MSTA and MTX).
283 * - Wait for the bus to become free or for a timeout to happen.
284 * - Disable the controller.
287 i2c_error_handler(struct i2c_softc *sc, int error)
291 i2c_write_reg(sc, I2C_STATUS_REG, 0);
292 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
293 wait_for_busbusy(sc, false);
294 i2c_write_reg(sc, I2C_CONTROL_REG, 0);
300 i2c_recover_getsda(void *ctx)
304 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active);
309 i2c_recover_setsda(void *ctx, int value)
312 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value);
316 i2c_recover_getscl(void *ctx)
320 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active);
326 i2c_recover_setscl(void *ctx, int value)
329 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value);
333 i2c_recover_bus(struct i2c_softc *sc)
335 struct iicrb_pin_access pins;
339 * If we have gpio pinmux config, reconfigure the pins to gpio mode,
340 * invoke iic_recover_bus which checks for a hung bus and bitbangs a
341 * recovery sequence if necessary, then configure the pins back to i2c
344 if (sc->rb_pinctl_idx == 0)
347 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx);
350 pins.getsda = i2c_recover_getsda;
351 pins.setsda = i2c_recover_setsda;
352 pins.getscl = i2c_recover_getscl;
353 pins.setscl = i2c_recover_setscl;
354 err = iic_recover_bus(&pins);
356 fdt_pinctrl_configure(sc->dev, 0);
362 i2c_probe(device_t dev)
365 if (!ofw_bus_status_okay(dev))
368 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
371 device_set_desc(dev, "Freescale i.MX I2C");
373 return (BUS_PROBE_DEFAULT);
377 i2c_attach(device_t dev)
380 struct i2c_softc *sc;
384 sc = device_get_softc(dev);
388 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
390 if (sc->res == NULL) {
391 device_printf(dev, "could not allocate resources");
395 sc->iicbus = device_add_child(dev, "iicbus", -1);
396 if (sc->iicbus == NULL) {
397 device_printf(dev, "could not add iicbus child");
401 /* Set up debug-enable sysctl. */
402 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
403 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
404 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0,
405 "Enable debug; 1=reads/writes, 2=add starts/stops");
408 * Set up for bus recovery using gpio pins, if the pinctrl and gpio
409 * properties are present. This is optional. If all the config data is
410 * not in place, we just don't do gpio bitbang bus recovery.
412 node = ofw_bus_get_node(sc->dev);
414 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios",
418 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios",
424 * Preset the gpio pins to output high (idle bus state). The signal
425 * won't actually appear on the pins until the bus recovery code changes
426 * the pinmux config from i2c to gpio.
428 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT);
429 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT);
430 gpio_pin_set_active(sc->rb_sclpin, true);
431 gpio_pin_set_active(sc->rb_sdapin, true);
434 * Obtain the index of pinctrl node for bus recovery using gpio pins,
435 * then confirm that pinctrl properties exist for that index and for the
436 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code
437 * will also do a bus recovery, so setting this value must be last.
439 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx);
441 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx);
442 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr))
443 sc->rb_pinctl_idx = cfgidx;
448 /* We don't do a hardware reset here because iicbus_attach() does it. */
450 /* Probe and attach the iicbus when interrupts are available. */
451 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
456 i2c_detach(device_t dev)
458 struct i2c_softc *sc;
461 sc = device_get_softc(dev);
463 if ((error = bus_generic_detach(sc->dev)) != 0) {
464 device_printf(sc->dev, "cannot detach child devices\n");
468 if (sc->iicbus != NULL)
469 device_delete_child(dev, sc->iicbus);
472 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
478 i2c_repeated_start(device_t dev, u_char slave, int timeout)
480 struct i2c_softc *sc;
483 sc = device_get_softc(dev);
485 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) {
486 return (IIC_EBUSERR);
490 * Set repeated start condition, delay (per reference manual, min 156nS)
491 * before writing slave address, wait for ack after write.
493 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA);
495 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
496 i2c_write_reg(sc, I2C_DATA_REG, slave);
498 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave);
499 error = wait_for_xfer(sc, true);
500 return (i2c_error_handler(sc, error));
504 i2c_start_ll(device_t dev, u_char slave, int timeout)
506 struct i2c_softc *sc;
509 sc = device_get_softc(dev);
511 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
512 DELAY(10); /* Delay for controller to sample bus state. */
513 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) {
514 return (i2c_error_handler(sc, IIC_EBUSERR));
516 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX);
517 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR)
518 return (i2c_error_handler(sc, error));
519 i2c_write_reg(sc, I2C_STATUS_REG, 0);
520 i2c_write_reg(sc, I2C_DATA_REG, slave);
522 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave);
523 error = wait_for_xfer(sc, true);
524 return (i2c_error_handler(sc, error));
528 i2c_start(device_t dev, u_char slave, int timeout)
530 struct i2c_softc *sc;
533 sc = device_get_softc(dev);
536 * Invoke the low-level code to put the bus into master mode and address
537 * the given slave. If that fails, idle the controller and attempt a
538 * bus recovery, and then try again one time. Signaling a start and
539 * addressing the slave is the only operation that a low-level driver
540 * can safely retry without any help from the upper layers that know
541 * more about the slave device.
543 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) {
544 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
545 if ((error = i2c_recover_bus(sc)) != 0)
547 error = i2c_start_ll(dev, slave, timeout);
553 i2c_stop(device_t dev)
555 struct i2c_softc *sc;
557 sc = device_get_softc(dev);
559 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
560 wait_for_busbusy(sc, false);
561 i2c_write_reg(sc, I2C_CONTROL_REG, 0);
562 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave);
567 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
569 struct i2c_softc *sc;
570 u_int busfreq, div, i, ipgfreq;
572 sc = device_get_softc(dev);
574 DEVICE_DEBUGF(sc, 1, "reset\n");
577 * Look up the divisor that gives the nearest speed that doesn't exceed
578 * the configured value for the bus.
580 ipgfreq = imx_ccm_ipg_hz();
581 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
582 div = howmany(ipgfreq, busfreq);
583 for (i = 0; i < nitems(clkdiv_table); i++) {
584 if (clkdiv_table[i].divisor >= div)
589 * Calculate roughly how long it will take to transfer a byte (which
590 * requires 9 clock cycles) at the new bus speed. This value is used to
591 * pause() while waiting for transfer-complete. With a 66MHz IPG clock
592 * and the actual i2c bus speeds that leads to, for nominal 100KHz and
593 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS.
595 busfreq = ipgfreq / clkdiv_table[i].divisor;
596 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq);
599 * Disable the controller (do the reset), and set the new clock divisor.
601 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
602 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
603 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode);
606 * Now that the controller is idle, perform bus recovery. If the bus
607 * isn't hung, this a fairly fast no-op.
609 return (i2c_recover_bus(sc));
613 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
615 struct i2c_softc *sc;
618 sc = device_get_softc(dev);
621 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len);
624 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
625 I2CCR_MSTA | I2CCR_TXAK);
627 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
629 /* Dummy read to prime the receiver. */
630 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
631 i2c_read_reg(sc, I2C_DATA_REG);
636 while (*read < len) {
637 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR)
639 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
641 if (*read == len - 2) {
642 /* NO ACK on last byte */
643 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
644 I2CCR_MSTA | I2CCR_TXAK);
645 } else if (*read == len - 1) {
646 /* Transfer done, signal stop. */
647 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
649 wait_for_busbusy(sc, false);
652 reg = i2c_read_reg(sc, I2C_DATA_REG);
653 DEBUGF(sc, 1, "0x%02x ", reg);
659 return (i2c_error_handler(sc, error));
663 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
665 struct i2c_softc *sc;
668 sc = device_get_softc(dev);
672 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len);
673 while (*sent < len) {
674 DEBUGF(sc, 1, "0x%02x ", *buf);
675 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
676 i2c_write_reg(sc, I2C_DATA_REG, *buf++);
677 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR)
682 return (i2c_error_handler(sc, error));