2 * Copyright (c) 2014 Ian Lepore
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
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21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Pin mux and pad control driver for imx5 and imx6.
32 * This driver implements the fdt_pinctrl interface for configuring the gpio and
33 * peripheral pins based on fdt configuration data.
35 * When the driver attaches, it walks the entire fdt tree and automatically
36 * configures the pins for each device which has a pinctrl-0 property and whose
37 * status is "okay". In addition it implements the fdt_pinctrl_configure()
38 * method which any other driver can call at any time to reconfigure its pins.
40 * The nature of the fsl,pins property in fdt data makes this driver's job very
41 * easy. Instead of representing each pin and pad configuration using symbolic
42 * properties such as pullup-enable="true" and so on, the data simply contains
43 * the addresses of the registers that control the pins, and the raw values to
44 * store in those registers.
46 * The imx5 and imx6 SoCs also have a small number of "general purpose
47 * registers" in the iomuxc device which are used to control an assortment
48 * of completely unrelated aspects of SoC behavior. This driver provides other
49 * drivers with direct access to those registers via simple accessor functions.
52 #include <sys/param.h>
53 #include <sys/systm.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
57 #include <sys/malloc.h>
60 #include <machine/bus.h>
62 #include <dev/ofw/openfirm.h>
63 #include <dev/ofw/ofw_bus.h>
64 #include <dev/ofw/ofw_bus_subr.h>
65 #include <dev/fdt/fdt_pinctrl.h>
67 #include <arm/freescale/imx/imx_iomuxvar.h>
68 #include <arm/freescale/imx/imx_machdep.h>
72 struct resource *mem_res;
76 static struct iomux_softc *iomux_sc;
78 static struct ofw_compat_data compat_data[] = {
79 {"fsl,imx6dl-iomuxc", true},
80 {"fsl,imx6q-iomuxc", true},
81 {"fsl,imx6sl-iomuxc", true},
82 {"fsl,imx6ul-iomuxc", true},
83 {"fsl,imx6sx-iomuxc", true},
84 {"fsl,imx53-iomuxc", true},
85 {"fsl,imx51-iomuxc", true},
90 * Each tuple in an fsl,pins property contains these fields.
101 #define PADCONF_NONE (1U << 31) /* Do not configure pad. */
102 #define PADCONF_SION (1U << 30) /* Force SION bit in mux register. */
103 #define PADMUX_SION (1U << 4) /* The SION bit in the mux register. */
105 static inline uint32_t
106 RD4(struct iomux_softc *sc, bus_size_t off)
109 return (bus_read_4(sc->mem_res, off));
113 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val)
116 bus_write_4(sc->mem_res, off, val);
120 iomux_configure_input(struct iomux_softc *sc, uint32_t reg, uint32_t val)
122 u_int select, mask, shift, width;
124 /* If register and value are zero, there is nothing to configure. */
125 if (reg == 0 && val == 0)
129 * If the config value has 0xff in the high byte it is encoded:
131 * | 0xff | shift | width | select |
132 * We need to mask out the old select value and OR in the new, using a
133 * mask of the given width and shifting the values up by shift.
135 if ((val & 0xff000000) == 0xff000000) {
136 select = val & 0x000000ff;
137 width = (val & 0x0000ff00) >> 8;
138 shift = (val & 0x00ff0000) >> 16;
139 mask = ((1u << width) - 1) << shift;
140 val = (RD4(sc, reg) & ~mask) | (select << shift);
146 iomux_configure_pins(device_t dev, phandle_t cfgxref)
148 struct iomux_softc *sc;
149 struct pincfg *cfgtuples, *cfg;
154 sc = device_get_softc(dev);
155 cfgnode = OF_node_from_xref(cfgxref);
156 ntuples = OF_getencprop_alloc_multi(cfgnode, "fsl,pins",
157 sizeof(*cfgtuples), (void **)&cfgtuples);
161 return (0); /* Empty property is not an error. */
162 for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) {
163 sion = (cfg->padconf_val & PADCONF_SION) ? PADMUX_SION : 0;
164 WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
165 iomux_configure_input(sc, cfg->input_reg, cfg->input_val);
166 if ((cfg->padconf_val & PADCONF_NONE) == 0)
167 WR4(sc, cfg->padconf_reg, cfg->padconf_val);
170 OF_getprop(cfgnode, "name", &name, sizeof(name));
171 printf("%16s: muxreg 0x%04x muxval 0x%02x "
172 "inpreg 0x%04x inpval 0x%02x "
173 "padreg 0x%04x padval 0x%08x\n",
174 name, cfg->mux_reg, cfg->mux_val | sion,
175 cfg->input_reg, cfg->input_val,
176 cfg->padconf_reg, cfg->padconf_val);
179 OF_prop_free(cfgtuples);
184 iomux_probe(device_t dev)
187 if (!ofw_bus_status_okay(dev))
190 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
193 device_set_desc(dev, "Freescale i.MX pin configuration");
194 return (BUS_PROBE_DEFAULT);
198 iomux_detach(device_t dev)
201 /* This device is always present. */
206 iomux_attach(device_t dev)
208 struct iomux_softc * sc;
211 sc = device_get_softc(dev);
214 switch (imx_soc_type()) {
216 sc->last_gpregaddr = 1 * sizeof(uint32_t);
219 sc->last_gpregaddr = 2 * sizeof(uint32_t);
225 sc->last_gpregaddr = 13 * sizeof(uint32_t);
228 sc->last_gpregaddr = 14 * sizeof(uint32_t);
231 device_printf(dev, "Unknown SoC type\n");
236 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
238 if (sc->mem_res == NULL) {
239 device_printf(dev, "Cannot allocate memory resources\n");
246 * Register as a pinctrl device, and call the convenience function that
247 * walks the entire device tree invoking FDT_PINCTRL_CONFIGURE() on any
248 * pinctrl-0 property cells whose xref phandle refers to a configuration
249 * that is a child node of our node in the tree.
251 * The pinctrl bindings documentation specifically mentions that the
252 * pinctrl device itself may have a pinctrl-0 property which contains
253 * static configuration to be applied at device init time. The tree
254 * walk will automatically handle this for us when it passes through our
257 fdt_pinctrl_register(dev, "fsl,pins");
258 fdt_pinctrl_configure_tree(dev);
264 imx_iomux_gpr_get(u_int regaddr)
266 struct iomux_softc * sc;
269 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
270 KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr,
271 ("%s bad regaddr %u, max %u", __FUNCTION__, regaddr,
272 sc->last_gpregaddr));
274 return (RD4(iomux_sc, regaddr));
278 imx_iomux_gpr_set(u_int regaddr, uint32_t val)
280 struct iomux_softc * sc;
283 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
284 KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr,
285 ("%s bad regaddr %u, max %u", __FUNCTION__, regaddr,
286 sc->last_gpregaddr));
288 WR4(iomux_sc, regaddr, val);
292 imx_iomux_gpr_set_masked(u_int regaddr, uint32_t clrbits, uint32_t setbits)
294 struct iomux_softc * sc;
298 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
299 KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr,
300 ("%s bad regaddr %u, max %u", __FUNCTION__, regaddr,
301 sc->last_gpregaddr));
303 val = RD4(iomux_sc, regaddr * 4);
304 val = (val & ~clrbits) | setbits;
305 WR4(iomux_sc, regaddr, val);
308 static device_method_t imx_iomux_methods[] = {
309 /* Device interface */
310 DEVMETHOD(device_probe, iomux_probe),
311 DEVMETHOD(device_attach, iomux_attach),
312 DEVMETHOD(device_detach, iomux_detach),
314 /* fdt_pinctrl interface */
315 DEVMETHOD(fdt_pinctrl_configure,iomux_configure_pins),
320 static driver_t imx_iomux_driver = {
323 sizeof(struct iomux_softc),
326 static devclass_t imx_iomux_devclass;
328 EARLY_DRIVER_MODULE(imx_iomux, simplebus, imx_iomux_driver,
329 imx_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE);