2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Vybrid Family Inter-Integrated Circuit (I2C)
31 * Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013
35 * This driver is based on the I2C driver for i.MX
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/malloc.h>
48 #include <sys/timeet.h>
49 #include <sys/timetc.h>
51 #include <dev/iicbus/iiconf.h>
52 #include <dev/iicbus/iicbus.h>
54 #include "iicbus_if.h"
56 #include <dev/ofw/openfirm.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/extres/clk/clk.h>
64 #include <machine/bus.h>
65 #include <machine/cpu.h>
66 #include <machine/intr.h>
68 #include <arm/freescale/vybrid/vf_common.h>
70 #define I2C_IBAD 0x0 /* I2C Bus Address Register */
71 #define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */
72 #define I2C_IBCR 0x2 /* I2C Bus Control Register */
73 #define IBCR_MDIS (1 << 7) /* Module disable. */
74 #define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */
75 #define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */
76 #define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */
77 #define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */
78 #define IBCR_RSTA (1 << 2) /* Repeat Start. */
79 #define IBCR_DMAEN (1 << 1) /* DMA Enable. */
80 #define I2C_IBSR 0x3 /* I2C Bus Status Register */
81 #define IBSR_TCF (1 << 7) /* Transfer complete. */
82 #define IBSR_IAAS (1 << 6) /* Addressed as a slave. */
83 #define IBSR_IBB (1 << 5) /* Bus busy. */
84 #define IBSR_IBAL (1 << 4) /* Arbitration Lost. */
85 #define IBSR_SRW (1 << 2) /* Slave Read/Write. */
86 #define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */
87 #define IBSR_RXAK (1 << 0) /* Received Acknowledge. */
88 #define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */
89 #define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */
90 #define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */
91 #define I2C_IBDBG 0x6 /* I2C Bus Debug Register */
94 #define vf_i2c_dbg(_sc, fmt, args...) \
95 device_printf((_sc)->dev, fmt, ##args)
97 #define vf_i2c_dbg(_sc, fmt, args...)
100 #define HW_UNKNOWN 0x00
101 #define HW_MVF600 0x01
102 #define HW_VF610 0x02
104 static int i2c_repeated_start(device_t, u_char, int);
105 static int i2c_start(device_t, u_char, int);
106 static int i2c_stop(device_t);
107 static int i2c_reset(device_t, u_char, u_char, u_char *);
108 static int i2c_read(device_t, char *, int, int *, int, int);
109 static int i2c_write(device_t, const char *, int, int *, int);
110 static phandle_t i2c_get_node(device_t, device_t);
112 struct i2c_div_type {
118 struct resource *res[2];
120 bus_space_handle_t bsh;
131 static struct resource_spec i2c_spec[] = {
132 { SYS_RES_MEMORY, 0, RF_ACTIVE },
133 { SYS_RES_IRQ, 0, RF_ACTIVE },
138 static struct i2c_div_type vf610_div_table[] = {
139 { 0x00, 20 }, { 0x01, 22 }, { 0x02, 24 }, { 0x03, 26 },
140 { 0x04, 28 }, { 0x05, 30 }, { 0x09, 32 }, { 0x06, 34 },
141 { 0x0A, 36 }, { 0x0B, 40 }, { 0x0C, 44 }, { 0x0D, 48 },
142 { 0x0E, 56 }, { 0x12, 64 }, { 0x13, 72 }, { 0x14, 80 },
143 { 0x15, 88 }, { 0x19, 96 }, { 0x16, 104 }, { 0x1A, 112 },
144 { 0x17, 128 }, { 0x1D, 160 }, { 0x1E, 192 }, { 0x22, 224 },
145 { 0x1F, 240 }, { 0x23, 256 }, { 0x24, 288 }, { 0x25, 320 },
146 { 0x26, 384 }, { 0x2A, 448 }, { 0x27, 480 }, { 0x2B, 512 },
147 { 0x2C, 576 }, { 0x2D, 640 }, { 0x2E, 768 }, { 0x32, 896 },
148 { 0x2F, 960 }, { 0x33, 1024 }, { 0x34, 1152 }, { 0x35, 1280 },
149 { 0x36, 1536 }, { 0x3A, 1792 }, { 0x37, 1920 }, { 0x3B, 2048 },
150 { 0x3C, 2304 }, { 0x3D, 2560 }, { 0x3E, 3072 }, { 0x3F, 3840 }
154 static const struct ofw_compat_data i2c_compat_data[] = {
155 {"fsl,mvf600-i2c", HW_MVF600},
156 {"fsl,vf610-i2c", HW_VF610},
161 i2c_probe(device_t dev)
164 if (!ofw_bus_status_okay(dev))
167 if (!ofw_bus_search_compatible(dev, i2c_compat_data)->ocd_data)
170 device_set_desc(dev, "Vybrid Family Inter-Integrated Circuit (I2C)");
171 return (BUS_PROBE_DEFAULT);
175 i2c_attach(device_t dev)
177 struct i2c_softc *sc;
183 sc = device_get_softc(dev);
185 sc->hwtype = ofw_bus_search_compatible(dev, i2c_compat_data)->ocd_data;
187 node = ofw_bus_get_node(dev);
189 error = clk_get_by_ofw_index(dev, node, 0, &sc->clock);
192 device_printf(dev, "Parent clock not found.\n");
194 if (OF_hasprop(node, "clock-frequency"))
195 OF_getencprop(node, "clock-frequency", &sc->freq,
202 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
204 error = bus_alloc_resources(dev, i2c_spec, sc->res);
206 mtx_destroy(&sc->mutex);
207 device_printf(dev, "could not allocate resources\n");
211 /* Memory interface */
212 sc->bst = rman_get_bustag(sc->res[0]);
213 sc->bsh = rman_get_bushandle(sc->res[0]);
215 WRITE1(sc, I2C_IBIC, IBIC_BIIE);
217 sc->iicbus = device_add_child(dev, "iicbus", -1);
218 if (sc->iicbus == NULL) {
219 device_printf(dev, "could not add iicbus child");
220 mtx_destroy(&sc->mutex);
221 bus_release_resources(dev, i2c_spec, sc->res);
225 bus_generic_attach(dev);
231 i2c_detach(device_t dev)
233 struct i2c_softc *sc;
236 sc = device_get_softc(dev);
238 error = bus_generic_detach(dev);
240 device_printf(dev, "cannot detach child devices.\n");
244 error = device_delete_child(dev, sc->iicbus);
246 device_printf(dev, "could not delete iicbus child.\n");
250 bus_release_resources(dev, i2c_spec, sc->res);
252 mtx_destroy(&sc->mutex);
257 /* Wait for transfer interrupt flag */
259 wait_for_iif(struct i2c_softc *sc)
265 if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
266 WRITE1(sc, I2C_IBSR, IBSR_IBIF);
272 return (IIC_ETIMEOUT);
275 /* Wait for free bus */
277 wait_for_nibb(struct i2c_softc *sc)
283 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0)
288 return (IIC_ETIMEOUT);
291 /* Wait for transfer complete+interrupt flag */
293 wait_for_icf(struct i2c_softc *sc)
299 if (READ1(sc, I2C_IBSR) & IBSR_TCF) {
300 if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
301 WRITE1(sc, I2C_IBSR, IBSR_IBIF);
308 return (IIC_ETIMEOUT);
312 i2c_repeated_start(device_t dev, u_char slave, int timeout)
314 struct i2c_softc *sc;
318 sc = device_get_softc(dev);
320 vf_i2c_dbg(sc, "i2c repeated start\n");
322 mtx_lock(&sc->mutex);
324 WRITE1(sc, I2C_IBAD, slave);
326 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) {
327 mtx_unlock(&sc->mutex);
328 return (IIC_EBUSERR);
331 /* Set repeated start condition */
334 reg = READ1(sc, I2C_IBCR);
335 reg |= (IBCR_RSTA | IBCR_IBIE);
336 WRITE1(sc, I2C_IBCR, reg);
340 /* Write target address - LSB is R/W bit */
341 WRITE1(sc, I2C_IBDR, slave);
343 error = wait_for_iif(sc);
345 mtx_unlock(&sc->mutex);
354 i2c_start(device_t dev, u_char slave, int timeout)
356 struct i2c_softc *sc;
360 sc = device_get_softc(dev);
362 vf_i2c_dbg(sc, "i2c start\n");
364 mtx_lock(&sc->mutex);
366 WRITE1(sc, I2C_IBAD, slave);
368 if (READ1(sc, I2C_IBSR) & IBSR_IBB) {
369 mtx_unlock(&sc->mutex);
370 vf_i2c_dbg(sc, "cant i2c start: IIC_EBUSBSY\n");
371 return (IIC_EBUSERR);
374 /* Set start condition */
375 reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE);
376 WRITE1(sc, I2C_IBCR, reg);
381 WRITE1(sc, I2C_IBCR, reg);
383 /* Write target address - LSB is R/W bit */
384 WRITE1(sc, I2C_IBDR, slave);
386 error = wait_for_iif(sc);
388 mtx_unlock(&sc->mutex);
390 vf_i2c_dbg(sc, "cant i2c start: iif error\n");
398 i2c_stop(device_t dev)
400 struct i2c_softc *sc;
402 sc = device_get_softc(dev);
404 vf_i2c_dbg(sc, "i2c stop\n");
406 mtx_lock(&sc->mutex);
408 WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE);
412 /* Reset controller if bus still busy after STOP */
413 if (wait_for_nibb(sc) == IIC_ETIMEOUT) {
414 WRITE1(sc, I2C_IBCR, IBCR_MDIS);
416 WRITE1(sc, I2C_IBCR, IBCR_NOACK);
418 mtx_unlock(&sc->mutex);
424 i2c_get_div_val(device_t dev)
426 struct i2c_softc *sc;
431 sc = device_get_softc(dev);
433 if (sc->hwtype == HW_MVF600)
437 return vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
439 error = clk_get_freq(sc->clock, &clk_freq);
441 device_printf(dev, "Could not get parent clock frequency. "
442 "Using default divider.\n");
443 return vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
446 for (i = 0; i < nitems(vf610_div_table) - 1; i++)
447 if ((clk_freq / vf610_div_table[i].div) <= sc->freq)
450 return vf610_div_table[i].reg_val;
452 sc = device_get_softc(dev);
454 if (sc->hwtype == HW_VF610)
462 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
464 struct i2c_softc *sc;
467 sc = device_get_softc(dev);
468 div = i2c_get_div_val(dev);
469 vf_i2c_dbg(sc, "Div val: %02x\n", div);
471 vf_i2c_dbg(sc, "i2c reset\n");
482 mtx_lock(&sc->mutex);
483 WRITE1(sc, I2C_IBCR, IBCR_MDIS);
487 WRITE1(sc, I2C_IBFD, div);
488 WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */
492 mtx_unlock(&sc->mutex);
498 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
500 struct i2c_softc *sc;
503 sc = device_get_softc(dev);
505 vf_i2c_dbg(sc, "i2c read\n");
509 mtx_lock(&sc->mutex);
513 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \
516 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL);
523 while (*read < len) {
524 error = wait_for_icf(sc);
526 mtx_unlock(&sc->mutex);
530 if ((*read == len - 2) && last) {
531 /* NO ACK on last byte */
532 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \
536 if ((*read == len - 1) && last) {
537 /* Transfer done, remove master bit */
538 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK);
541 *buf++ = READ1(sc, I2C_IBDR);
544 mtx_unlock(&sc->mutex);
550 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
552 struct i2c_softc *sc;
555 sc = device_get_softc(dev);
557 vf_i2c_dbg(sc, "i2c write\n");
561 mtx_lock(&sc->mutex);
562 while (*sent < len) {
564 WRITE1(sc, I2C_IBDR, *buf++);
566 error = wait_for_iif(sc);
568 mtx_unlock(&sc->mutex);
574 mtx_unlock(&sc->mutex);
580 i2c_get_node(device_t bus, device_t dev)
583 return ofw_bus_get_node(bus);
586 static device_method_t i2c_methods[] = {
587 DEVMETHOD(device_probe, i2c_probe),
588 DEVMETHOD(device_attach, i2c_attach),
589 DEVMETHOD(device_detach, i2c_detach),
591 DEVMETHOD(ofw_bus_get_node, i2c_get_node),
593 DEVMETHOD(iicbus_callback, iicbus_null_callback),
594 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
595 DEVMETHOD(iicbus_start, i2c_start),
596 DEVMETHOD(iicbus_stop, i2c_stop),
597 DEVMETHOD(iicbus_reset, i2c_reset),
598 DEVMETHOD(iicbus_read, i2c_read),
599 DEVMETHOD(iicbus_write, i2c_write),
600 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
605 static driver_t i2c_driver = {
608 sizeof(struct i2c_softc),
611 static devclass_t i2c_devclass;
613 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
614 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
615 DRIVER_MODULE(ofw_iicbus, i2c, ofw_iicbus_driver, ofw_iicbus_devclass, 0, 0);