1 /* $NetBSD: frame.h,v 1.6 2003/10/05 19:44:58 matt Exp $ */
4 * Copyright (c) 1994-1997 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
8 * This code is derived from software written for Brini by Mark Brinicombe
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 #ifndef _MACHINE_ASMACROS_H_
41 #define _MACHINE_ASMACROS_H_
43 #include <machine/asm.h>
48 #include "opt_global.h"
51 * ASM macros for pushing and pulling trapframes from the stack
53 * These macros are used to handle the irqframe and trapframe structures
58 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
59 * Since the current mode is used, the SVC lr field is not defined.
61 * NOTE: r13 and r14 are stored separately as a work around for the
62 * SA110 rev 2 STM^ bug
66 str lr, [sp, #-4]!; /* Push the return address */ \
67 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
68 stmia sp, {r0-r12}; /* Push the user mode registers */ \
69 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
70 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
71 mov r0, r0; /* NOP for previous instruction */ \
72 mrs r0, spsr_all; /* Put the SPSR on the stack */ \
74 ldr r0, =ARM_RAS_START; \
77 mov r1, #0xffffffff; \
81 str lr, [sp, #-4]!; /* Push the return address */ \
82 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
83 stmia sp, {r0-r12}; /* Push the user mode registers */ \
84 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
85 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
86 mov r0, r0; /* NOP for previous instruction */ \
87 mrs r0, spsr_all; /* Put the SPSR on the stack */ \
92 * PULLFRAME - macro to pull a trap frame from the stack in the current mode
93 * Since the current mode is used, the SVC lr field is ignored.
98 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
100 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
101 mov r0, r0; /* NOP for previous instruction */ \
102 add sp, sp, #(4*17); /* Adjust the stack pointer */ \
103 ldr lr, [sp], #0x0004; /* Pull the return address */
106 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
109 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
110 mov r0, r0; /* NOP for previous instruction */ \
111 add sp, sp, #(4*17); /* Adjust the stack pointer */ \
112 ldr lr, [sp], #0x0004; /* Pull the return address */
116 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
117 * This should only be used if the processor is not currently in SVC32
118 * mode. The processor mode is switched to SVC mode and the trap frame is
119 * stored. The SVC lr field is used to store the previous value of
122 * NOTE: r13 and r14 are stored separately as a work around for the
123 * SA110 rev 2 STM^ bug
125 #ifdef ARM_TP_ADDRESS
126 #define PUSHFRAMEINSVC \
127 stmdb sp, {r0-r3}; /* Save 4 registers */ \
128 mov r0, lr; /* Save xxx32 r14 */ \
129 mov r1, sp; /* Save xxx32 sp */ \
130 mrs r3, spsr; /* Save xxx32 spsr */ \
131 mrs r2, cpsr; /* Get the CPSR */ \
132 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
133 orr r2, r2, #(PSR_SVC32_MODE); \
134 msr cpsr_c, r2; /* Punch into SVC mode */ \
135 mov r2, sp; /* Save SVC sp */ \
136 str r0, [sp, #-4]!; /* Push return address */ \
137 str lr, [sp, #-4]!; /* Push SVC lr */ \
138 str r2, [sp, #-4]!; /* Push SVC sp */ \
139 msr spsr_all, r3; /* Restore correct spsr */ \
140 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
141 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
142 stmia sp, {r0-r12}; /* Push the user mode registers */ \
143 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
144 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
145 mov r0, r0; /* NOP for previous instruction */ \
146 ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \
147 ldr r4, [r5, #4]; /* reset it to point at the */ \
148 cmp r4, #0xffffffff; /* end of memory if necessary; */ \
149 movne r1, #0xffffffff; /* leave value in r4 for later */ \
150 strne r1, [r5, #4]; /* comparision against PC. */ \
151 ldr r3, [r5]; /* Retrieve global RAS_START */ \
152 cmp r3, #0; /* and reset it if non-zero. */ \
153 movne r1, #0; /* If non-zero RAS_START and */ \
154 strne r1, [r5]; /* PC was lower than RAS_END, */ \
155 ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \
156 cmpne r4, r1; /* execution later resumes at */ \
157 strhi r3, [r0, #16]; /* the RAS_START location. */ \
161 #define PUSHFRAMEINSVC \
162 stmdb sp, {r0-r3}; /* Save 4 registers */ \
163 mov r0, lr; /* Save xxx32 r14 */ \
164 mov r1, sp; /* Save xxx32 sp */ \
165 mrs r3, spsr; /* Save xxx32 spsr */ \
166 mrs r2, cpsr; /* Get the CPSR */ \
167 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
168 orr r2, r2, #(PSR_SVC32_MODE); \
169 msr cpsr_c, r2; /* Punch into SVC mode */ \
170 mov r2, sp; /* Save SVC sp */ \
171 str r0, [sp, #-4]!; /* Push return address */ \
172 str lr, [sp, #-4]!; /* Push SVC lr */ \
173 str r2, [sp, #-4]!; /* Push SVC sp */ \
174 msr spsr_all, r3; /* Restore correct spsr */ \
175 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
176 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
177 stmia sp, {r0-r12}; /* Push the user mode registers */ \
178 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
179 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
180 mov r0, r0; /* NOP for previous instruction */ \
181 mrs r0, spsr_all; /* Put the SPSR on the stack */ \
186 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
187 * in SVC32 mode and restore the saved processor mode and PC.
188 * This should be used when the SVC lr register needs to be restored on
192 #ifdef ARM_TP_ADDRESS
193 #define PULLFRAMEFROMSVCANDEXIT \
194 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
195 msr spsr_all, r0; /* restore SPSR */ \
196 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
197 mov r0, r0; /* NOP for previous instruction */ \
198 add sp, sp, #(4*15); /* Adjust the stack pointer */ \
199 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
201 #define PULLFRAMEFROMSVCANDEXIT \
202 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
203 msr spsr_all, r0; /* restore SPSR */ \
205 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
206 mov r0, r0; /* NOP for previous instruction */ \
207 add sp, sp, #(4*15); /* Adjust the stack pointer */ \
208 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
215 .type name, %object ; \
220 #define GET_CURTHREAD_PTR(tmp) \
221 mrc p15, 0, tmp, c13, c0, 4; \
222 add tmp, tmp, #(PC_CURTHREAD)
224 #define AST_LOCALS ;\
226 .word _C_LABEL(__pcpu) + PC_CURTHREAD
228 #define GET_CURTHREAD_PTR(tmp) \
233 ldr r0, [sp] /* Get the SPSR from stack */ ;\
234 mrs r4, cpsr /* save CPSR */ ;\
235 orr r1, r4, #(I32_bit|F32_bit) ;\
236 msr cpsr_c, r1 /* Disable interrupts */ ;\
237 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
238 teq r0, #(PSR_USR32_MODE) ;\
239 bne 2f /* Nope, get out now */ ;\
240 bic r4, r4, #(I32_bit|F32_bit) ;\
241 1: GET_CURTHREAD_PTR(r5) ;\
243 ldr r1, [r5, #(TD_FLAGS)] ;\
244 and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\
245 teq r1, #0x00000000 ;\
246 beq 2f /* Nope. Just bail */ ;\
247 msr cpsr_c, r4 /* Restore interrupts */ ;\
249 bl _C_LABEL(ast) /* ast(frame) */ ;\
250 orr r0, r4, #(I32_bit|F32_bit) ;\
259 #endif /* !_MACHINE_ASMACROS_H_ */