1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * This code is derived from software written for Brini by Mark Brinicombe
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Brini.
22 * 4. The name of Brini may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef _MACHINE_ATOMIC_V4_H_
40 #define _MACHINE_ATOMIC_V4_H_
42 #ifndef _MACHINE_ATOMIC_H_
43 #error Do not include this file directly, use <machine/atomic.h>
47 #define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory")
48 #define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
51 #error Only use this file with ARMv5 and earlier
58 #define __with_interrupts_disabled(expr) \
60 u_int cpsr_save, tmp; \
65 "msr cpsr_fsxc, %1;" \
66 : "=r" (cpsr_save), "=r" (tmp) \
67 : "I" (PSR_I | PSR_F) \
77 static __inline uint32_t
78 __swp(uint32_t val, volatile uint32_t *ptr)
80 __asm __volatile("swp %0, %2, [%3]"
81 : "=&r" (val), "=m" (*ptr)
82 : "r" (val), "r" (ptr), "m" (*ptr)
89 #define ARM_HAVE_ATOMIC64
92 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
94 __with_interrupts_disabled(*p += val);
98 atomic_add_64(volatile u_int64_t *p, u_int64_t val)
100 __with_interrupts_disabled(*p += val);
104 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
106 __with_interrupts_disabled(*address &= ~clearmask);
110 atomic_clear_64(volatile uint64_t *address, uint64_t clearmask)
112 __with_interrupts_disabled(*address &= ~clearmask);
116 atomic_fcmpset_32(volatile u_int32_t *p, volatile u_int32_t *cmpval, volatile u_int32_t newval)
120 __with_interrupts_disabled(
135 atomic_fcmpset_64(volatile u_int64_t *p, volatile u_int64_t *cmpval, volatile u_int64_t newval)
139 __with_interrupts_disabled(
152 static __inline u_int32_t
153 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
157 __with_interrupts_disabled(
169 static __inline u_int64_t
170 atomic_cmpset_64(volatile u_int64_t *p, volatile u_int64_t cmpval, volatile u_int64_t newval)
174 __with_interrupts_disabled(
187 static __inline uint32_t
188 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
192 __with_interrupts_disabled(
200 static __inline uint64_t
201 atomic_fetchadd_64(volatile uint64_t *p, uint64_t v)
205 __with_interrupts_disabled(
213 static __inline uint64_t
214 atomic_load_64(volatile uint64_t *p)
218 __with_interrupts_disabled(value = *p);
223 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
225 __with_interrupts_disabled(*address |= setmask);
229 atomic_set_64(volatile uint64_t *address, uint64_t setmask)
231 __with_interrupts_disabled(*address |= setmask);
235 atomic_store_64(volatile uint64_t *p, uint64_t value)
237 __with_interrupts_disabled(*p = value);
241 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
243 __with_interrupts_disabled(*p -= val);
247 atomic_subtract_64(volatile u_int64_t *p, u_int64_t val)
249 __with_interrupts_disabled(*p -= val);
255 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
257 int start, ras_start = ARM_RAS_START;
259 __asm __volatile("1:\n"
270 "mov %1, #0xffffffff\n"
272 : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
277 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
279 int start, ras_start = ARM_RAS_START;
281 __asm __volatile("1:\n"
292 "mov %1, #0xffffffff\n"
294 : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)
299 static __inline u_int32_t
300 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
302 register int done, ras_start = ARM_RAS_START;
304 __asm __volatile("1:\n"
315 "mov %1, #0xffffffff\n"
319 : "+r" (ras_start), "=r" (done)
320 ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory");
324 static __inline uint32_t
325 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
327 uint32_t start, tmp, ras_start = ARM_RAS_START;
329 __asm __volatile("1:\n"
341 "mov %2, #0xffffffff\n"
343 : "+r" (ras_start), "=r" (start), "=r" (tmp), "+r" (p), "+r" (v)
349 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
351 int start, ras_start = ARM_RAS_START;
353 __asm __volatile("1:\n"
364 "mov %1, #0xffffffff\n"
367 : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
372 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
374 int start, ras_start = ARM_RAS_START;
376 __asm __volatile("1:\n"
387 "mov %1, #0xffffffff\n"
390 : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
396 static __inline uint32_t
397 atomic_readandclear_32(volatile u_int32_t *p)
400 return (__swp(0, p));
403 static __inline uint32_t
404 atomic_swap_32(volatile u_int32_t *p, u_int32_t v)
407 return (__swp(v, p));
410 #define atomic_fcmpset_rel_32 atomic_fcmpset_32
411 #define atomic_fcmpset_acq_32 atomic_fcmpset_32
412 #define atomic_fcmpset_rel_64 atomic_fcmpset_64
413 #define atomic_fcmpset_acq_64 atomic_fcmpset_64
414 #define atomic_fcmpset_acq_long atomic_fcmpset_long
415 #define atomic_fcmpset_rel_long atomic_fcmpset_long
416 #define atomic_cmpset_rel_32 atomic_cmpset_32
417 #define atomic_cmpset_acq_32 atomic_cmpset_32
418 #define atomic_cmpset_rel_64 atomic_cmpset_64
419 #define atomic_cmpset_acq_64 atomic_cmpset_64
420 #define atomic_set_rel_32 atomic_set_32
421 #define atomic_set_acq_32 atomic_set_32
422 #define atomic_clear_rel_32 atomic_clear_32
423 #define atomic_clear_acq_32 atomic_clear_32
424 #define atomic_add_rel_32 atomic_add_32
425 #define atomic_add_acq_32 atomic_add_32
426 #define atomic_subtract_rel_32 atomic_subtract_32
427 #define atomic_subtract_acq_32 atomic_subtract_32
428 #define atomic_store_rel_32 atomic_store_32
429 #define atomic_store_rel_long atomic_store_long
430 #define atomic_load_acq_32 atomic_load_32
431 #define atomic_load_acq_long atomic_load_long
432 #define atomic_add_acq_long atomic_add_long
433 #define atomic_add_rel_long atomic_add_long
434 #define atomic_subtract_acq_long atomic_subtract_long
435 #define atomic_subtract_rel_long atomic_subtract_long
436 #define atomic_clear_acq_long atomic_clear_long
437 #define atomic_clear_rel_long atomic_clear_long
438 #define atomic_set_acq_long atomic_set_long
439 #define atomic_set_rel_long atomic_set_long
440 #define atomic_cmpset_acq_long atomic_cmpset_long
441 #define atomic_cmpset_rel_long atomic_cmpset_long
442 #define atomic_load_acq_long atomic_load_long
443 #undef __with_interrupts_disabled
446 atomic_add_long(volatile u_long *p, u_long v)
449 atomic_add_32((volatile uint32_t *)p, v);
453 atomic_clear_long(volatile u_long *p, u_long v)
456 atomic_clear_32((volatile uint32_t *)p, v);
460 atomic_cmpset_long(volatile u_long *dst, u_long old, u_long newe)
463 return (atomic_cmpset_32((volatile uint32_t *)dst, old, newe));
466 static __inline u_long
467 atomic_fcmpset_long(volatile u_long *dst, u_long *old, u_long newe)
470 return (atomic_fcmpset_32((volatile uint32_t *)dst,
471 (uint32_t *)old, newe));
474 static __inline u_long
475 atomic_fetchadd_long(volatile u_long *p, u_long v)
478 return (atomic_fetchadd_32((volatile uint32_t *)p, v));
482 atomic_readandclear_long(volatile u_long *p)
485 atomic_readandclear_32((volatile uint32_t *)p);
489 atomic_set_long(volatile u_long *p, u_long v)
492 atomic_set_32((volatile uint32_t *)p, v);
496 atomic_subtract_long(volatile u_long *p, u_long v)
499 atomic_subtract_32((volatile uint32_t *)p, v);
503 * ARMv5 does not support SMP. For both kernel and user modes, only a
504 * compiler barrier is needed for fences, since CPU is always
508 atomic_thread_fence_acq(void)
515 atomic_thread_fence_rel(void)
522 atomic_thread_fence_acq_rel(void)
529 atomic_thread_fence_seq_cst(void)
535 #endif /* _MACHINE_ATOMIC_H_ */