1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * This code is derived from software written for Brini by Mark Brinicombe
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Brini.
22 * 4. The name of Brini may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef _MACHINE_ATOMIC_H_
40 #define _MACHINE_ATOMIC_H_
44 #include <sys/types.h>
47 #include <machine/sysarch.h>
51 #define I32_bit (1 << 7) /* IRQ disable */
54 #define F32_bit (1 << 6) /* FIQ disable */
57 #define __with_interrupts_disabled(expr) \
59 u_int cpsr_save, tmp; \
65 : "=r" (cpsr_save), "=r" (tmp) \
66 : "I" (I32_bit | F32_bit) \
76 static __inline uint32_t
77 __swp(uint32_t val, volatile uint32_t *ptr)
79 __asm __volatile("swp %0, %2, [%3]"
80 : "=&r" (val), "=m" (*ptr)
81 : "r" (val), "r" (ptr), "m" (*ptr)
89 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
91 __with_interrupts_disabled(*address |= setmask);
95 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
97 __with_interrupts_disabled(*address &= ~clearmask);
100 static __inline u_int32_t
101 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
105 __with_interrupts_disabled(
118 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
120 __with_interrupts_disabled(*p += val);
124 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
126 __with_interrupts_disabled(*p -= val);
129 static __inline uint32_t
130 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
134 __with_interrupts_disabled(
144 static __inline u_int32_t
145 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
147 register int done, ras_start = ARM_RAS_START;
149 __asm __volatile("1:\n"
160 "mov %1, #0xffffffff\n"
164 : "+r" (ras_start), "=r" (done)
165 ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "memory");
170 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
172 int start, ras_start = ARM_RAS_START;
174 __asm __volatile("1:\n"
185 "mov %1, #0xffffffff\n"
187 : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
192 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
194 int start, ras_start = ARM_RAS_START;
196 __asm __volatile("1:\n"
207 "mov %1, #0xffffffff\n"
210 : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
215 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
217 int start, ras_start = ARM_RAS_START;
219 __asm __volatile("1:\n"
230 "mov %1, #0xffffffff\n"
233 : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
238 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
240 int start, ras_start = ARM_RAS_START;
242 __asm __volatile("1:\n"
253 "mov %1, #0xffffffff\n"
255 : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)
260 static __inline uint32_t
261 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
263 uint32_t start, ras_start = ARM_RAS_START;
265 __asm __volatile("1:\n"
276 "mov %3, #0xffffffff\n"
278 : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (v)
287 atomic_load_32(volatile uint32_t *v)
294 atomic_store_32(volatile uint32_t *dst, uint32_t src)
299 static __inline uint32_t
300 atomic_readandclear_32(volatile u_int32_t *p)
303 return (__swp(0, p));
306 #undef __with_interrupts_disabled
310 #define atomic_add_long(p, v) \
311 atomic_add_32((volatile u_int *)(p), (u_int)(v))
312 #define atomic_add_acq_long atomic_add_long
313 #define atomic_add_rel_long atomic_add_long
314 #define atomic_subtract_long(p, v) \
315 atomic_subtract_32((volatile u_int *)(p), (u_int)(v))
316 #define atomic_subtract_acq_long atomic_subtract_long
317 #define atomic_subtract_rel_long atomic_subtract_long
318 #define atomic_clear_long(p, v) \
319 atomic_clear_32((volatile u_int *)(p), (u_int)(v))
320 #define atomic_clear_acq_long atomic_clear_long
321 #define atomic_clear_rel_long atomic_clear_long
322 #define atomic_set_long(p, v) \
323 atomic_set_32((volatile u_int *)(p), (u_int)(v))
324 #define atomic_set_acq_long atomic_set_long
325 #define atomic_set_rel_long atomic_set_long
326 #define atomic_cmpset_long(dst, old, new) \
327 atomic_cmpset_32((volatile u_int *)(dst), (u_int)(old), (u_int)(new))
328 #define atomic_cmpset_acq_long atomic_cmpset_long
329 #define atomic_cmpset_rel_long atomic_cmpset_long
330 #define atomic_fetchadd_long(p, v) \
331 atomic_fetchadd_32((volatile u_int *)(p), (u_int)(v))
332 #define atomic_readandclear_long(p) \
333 atomic_readandclear_long((volatile u_int *)(p))
334 #define atomic_load_long(p) \
335 atomic_load_32((volatile u_int *)(p))
336 #define atomic_load_acq_long atomic_load_long
337 #define atomic_store_rel_long(p, v) \
338 atomic_store_rel_32((volatile u_int *)(p), (u_int)(v))
341 #define atomic_clear_ptr atomic_clear_32
342 #define atomic_set_ptr atomic_set_32
343 #define atomic_cmpset_ptr atomic_cmpset_32
344 #define atomic_cmpset_rel_ptr atomic_cmpset_ptr
345 #define atomic_cmpset_acq_ptr atomic_cmpset_ptr
346 #define atomic_store_ptr atomic_store_32
347 #define atomic_store_rel_ptr atomic_store_ptr
349 #define atomic_add_int atomic_add_32
350 #define atomic_add_acq_int atomic_add_int
351 #define atomic_add_rel_int atomic_add_int
352 #define atomic_subtract_int atomic_subtract_32
353 #define atomic_subtract_acq_int atomic_subtract_int
354 #define atomic_subtract_rel_int atomic_subtract_int
355 #define atomic_clear_int atomic_clear_32
356 #define atomic_clear_acq_int atomic_clear_int
357 #define atomic_clear_rel_int atomic_clear_int
358 #define atomic_set_int atomic_set_32
359 #define atomic_set_acq_int atomic_set_int
360 #define atomic_set_rel_int atomic_set_int
361 #define atomic_cmpset_int atomic_cmpset_32
362 #define atomic_cmpset_acq_int atomic_cmpset_int
363 #define atomic_cmpset_rel_int atomic_cmpset_int
364 #define atomic_fetchadd_int atomic_fetchadd_32
365 #define atomic_readandclear_int atomic_readandclear_32
366 #define atomic_load_acq_int atomic_load_32
367 #define atomic_store_rel_int atomic_store_32
369 #define atomic_add_acq_32 atomic_add_32
370 #define atomic_add_rel_32 atomic_add_32
371 #define atomic_subtract_acq_32 atomic_subtract_32
372 #define atomic_subtract_rel_32 atomic_subtract_32
373 #define atomic_clear_acq_32 atomic_clear_32
374 #define atomic_clear_rel_32 atomic_clear_32
375 #define atomic_set_acq_32 atomic_set_32
376 #define atomic_set_rel_32 atomic_set_32
377 #define atomic_cmpset_acq_32 atomic_cmpset_32
378 #define atomic_cmpset_rel_32 atomic_cmpset_32
379 #define atomic_load_acq_32 atomic_load_32
380 #define atomic_store_rel_32 atomic_store_32
382 #endif /* _MACHINE_ATOMIC_H_ */