1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * This code is derived from software written for Brini by Mark Brinicombe
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Brini.
22 * 4. The name of Brini may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef _MACHINE_ATOMIC_H_
40 #define _MACHINE_ATOMIC_H_
46 #include <sys/types.h>
49 #define I32_bit (1 << 7) /* IRQ disable */
52 #define F32_bit (1 << 6) /* FIQ disable */
55 #define __with_interrupts_disabled(expr) \
57 u_int cpsr_save, tmp; \
63 : "=r" (cpsr_save), "=r" (tmp) \
74 #define ARM_RAS_START 0xe0000004
75 #define ARM_RAS_END 0xe0000008
77 static __inline uint32_t
78 __swp(uint32_t val, volatile uint32_t *ptr)
80 __asm __volatile("swp %0, %2, [%3]"
81 : "=&r" (val), "=m" (*ptr)
82 : "r" (val), "r" (ptr), "m" (*ptr)
90 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
92 __with_interrupts_disabled(*address |= setmask);
96 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
98 __with_interrupts_disabled(*address &= ~clearmask);
101 static __inline u_int32_t
102 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
106 __with_interrupts_disabled(
119 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
121 __with_interrupts_disabled(*p += val);
125 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
127 __with_interrupts_disabled(*p -= val);
130 static __inline uint32_t
131 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
135 __with_interrupts_disabled(
145 static __inline u_int32_t
146 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
148 register int done, ras_start;
150 __asm __volatile("1:\n"
151 "mov %0, #0xe0000008\n"
155 "mov %0, #0xe0000004\n"
165 : "=r" (ras_start), "=r" (done)
166 ,"=m" (*p), "+r" (cmpval), "+r" (newval)
172 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
174 int ras_start, start;
176 __asm __volatile("1:\n"
177 "mov %0, #0xe0000008\n"
181 "mov %0, #0xe0000004\n"
189 : "=r" (ras_start), "=r" (start), "=m" (*p), "+r" (val)
194 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
196 int ras_start, start;
198 __asm __volatile("1:\n"
199 "mov %0, #0xe0000008\n"
203 "mov %0, #0xe0000004\n"
212 : "=r" (ras_start), "=r" (start), "=m" (*p), "+r" (val)
217 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
219 int ras_start, start;
221 __asm __volatile("1:\n"
222 "mov %0, #0xe0000008\n"
226 "mov %0, #0xe0000004\n"
235 : "=r" (ras_start), "=r" (start), "=m" (*address), "+r" (setmask)
240 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
242 int ras_start, start;
244 __asm __volatile("1:\n"
245 "mov %0, #0xe0000008\n"
249 "mov %0, #0xe0000004\n"
257 : "=r" (ras_start), "=r" (start), "=m" (*address), "+r" (clearmask)
262 static __inline uint32_t
263 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
265 uint32_t ras_start, start;
267 __asm __volatile("1:\n"
268 "mov %0, #0xe0000008\n"
272 "mov %0, #0xe0000004\n"
280 : "=r" (ras_start), "=r" (start), "=m" (*p), "+r" (v)
289 atomic_load_32(volatile uint32_t *v)
296 atomic_store_32(volatile uint32_t *dst, uint32_t src)
301 static __inline uint32_t
302 atomic_readandclear_32(volatile u_int32_t *p)
305 return (__swp(0, p));
308 #undef __with_interrupts_disabled
313 #define atomic_set_rel_int atomic_set_32
314 #define atomic_set_int atomic_set_32
315 #define atomic_readandclear_int atomic_readandclear_32
316 #define atomic_clear_int atomic_clear_32
317 #define atomic_subtract_int atomic_subtract_32
318 #define atomic_subtract_rel_int atomic_subtract_32
319 #define atomic_subtract_acq_int atomic_subtract_32
320 #define atomic_add_int atomic_add_32
321 #define atomic_add_rel_int atomic_add_32
322 #define atomic_add_acq_int atomic_add_32
323 #define atomic_cmpset_int atomic_cmpset_32
324 #define atomic_cmpset_rel_int atomic_cmpset_32
325 #define atomic_cmpset_rel_ptr atomic_cmpset_ptr
326 #define atomic_cmpset_acq_int atomic_cmpset_32
327 #define atomic_cmpset_acq_ptr atomic_cmpset_ptr
328 #define atomic_store_rel_ptr atomic_store_ptr
329 #define atomic_store_rel_int atomic_store_32
330 #define atomic_cmpset_rel_32 atomic_cmpset_32
331 #define atomic_cmpset_rel_ptr atomic_cmpset_ptr
332 #define atomic_load_acq_int atomic_load_32
333 #define atomic_clear_ptr atomic_clear_32
334 #define atomic_store_ptr atomic_store_32
335 #define atomic_cmpset_ptr atomic_cmpset_32
336 #define atomic_set_ptr atomic_set_32
337 #define atomic_fetchadd_int atomic_fetchadd_32
339 #endif /* _MACHINE_ATOMIC_H_ */