1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * This code is derived from software written for Brini by Mark Brinicombe
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Brini.
22 * 4. The name of Brini may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef _MACHINE_ATOMIC_H_
40 #define _MACHINE_ATOMIC_H_
46 #include <sys/types.h>
49 #define I32_bit (1 << 7) /* IRQ disable */
52 #define F32_bit (1 << 6) /* FIQ disable */
55 #define __with_interrupts_disabled(expr) \
57 u_int cpsr_save, tmp; \
63 : "=r" (cpsr_save), "=r" (tmp) \
74 #define ARM_RAS_START 0xe0000004
75 #define ARM_RAS_END 0xe0000008
77 static __inline uint32_t
78 __swp(uint32_t val, volatile uint32_t *ptr)
80 __asm __volatile("swp %0, %1, [%2]"
81 : "=&r" (val) : "r" (val) , "r" (ptr) : "memory");
88 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
90 __with_interrupts_disabled(*address |= setmask);
94 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
96 __with_interrupts_disabled(*address &= ~clearmask);
99 static __inline u_int32_t
100 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
104 __with_interrupts_disabled(
117 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
119 __with_interrupts_disabled(*p += val);
123 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
125 __with_interrupts_disabled(*p -= val);
130 static __inline u_int32_t
131 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
133 register int done, ras_start;
135 __asm __volatile("1:\n"
136 "mov %0, #0xe0000008\n"
140 "mov %0, #0xe0000004\n"
150 : "=r" (ras_start), "=r" (done)
151 ,"+r" (p), "+r" (cmpval), "+r" (newval));
156 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
158 int ras_start, start;
160 __asm __volatile("1:\n"
161 "mov %0, #0xe0000008\n"
165 "mov %0, #0xe0000004\n"
173 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val));
177 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
179 int ras_start, start;
181 __asm __volatile("1:\n"
182 "mov %0, #0xe0000008\n"
186 "mov %0, #0xe0000004\n"
195 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val));
199 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
201 int ras_start, start;
203 __asm __volatile("1:\n"
204 "mov %0, #0xe0000008\n"
208 "mov %0, #0xe0000004\n"
217 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask));
221 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
223 int ras_start, start;
225 __asm __volatile("1:\n"
226 "mov %0, #0xe0000008\n"
230 "mov %0, #0xe0000004\n"
238 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask));
244 atomic_load_32(volatile uint32_t *v)
251 atomic_store_32(volatile uint32_t *dst, uint32_t src)
256 static __inline uint32_t
257 atomic_readandclear_32(volatile u_int32_t *p)
260 return (__swp(0, p));
263 #undef __with_interrupts_disabled
268 #define atomic_set_rel_int atomic_set_32
269 #define atomic_set_int atomic_set_32
270 #define atomic_readandclear_int atomic_readandclear_32
271 #define atomic_clear_int atomic_clear_32
272 #define atomic_subtract_int atomic_subtract_32
273 #define atomic_subtract_rel_int atomic_subtract_32
274 #define atomic_subtract_acq_int atomic_subtract_32
275 #define atomic_add_int atomic_add_32
276 #define atomic_add_rel_int atomic_add_32
277 #define atomic_add_acq_int atomic_add_32
278 #define atomic_cmpset_int atomic_cmpset_32
279 #define atomic_cmpset_rel_int atomic_cmpset_32
280 #define atomic_cmpset_rel_ptr atomic_cmpset_ptr
281 #define atomic_cmpset_acq_int atomic_cmpset_32
282 #define atomic_cmpset_acq_ptr atomic_cmpset_ptr
283 #define atomic_store_rel_ptr atomic_store_ptr
284 #define atomic_store_rel_int atomic_store_32
285 #define atomic_cmpset_rel_32 atomic_cmpset_32
286 #define atomic_smpset_rel_ptr atomic_cmpset_ptr
287 #define atomic_load_acq_int atomic_load_32
288 #define atomic_clear_ptr(ptr, bit) atomic_clear_32( \
289 (volatile uint32_t *)ptr, (uint32_t)bit)
290 #define atomic_store_ptr(ptr, bit) atomic_store_32( \
291 (volatile uint32_t *)ptr, (uint32_t)bit)
292 #define atomic_cmpset_ptr(dst, exp, s) atomic_cmpset_32( \
293 (volatile uint32_t *)dst, (uint32_t)exp, (uint32_t)s)
294 #define atomic_set_ptr(ptr, src) atomic_set_32( \
295 (volatile uint32_t *)ptr, (uint32_t)src)
297 #endif /* _MACHINE_ATOMIC_H_ */