sys/arm/include/cpu-v6.h

   1 /*-
   2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
   3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 #ifndef MACHINE_CPU_V6_H
  30 #define MACHINE_CPU_V6_H
  31
  32 /* There are no user serviceable parts here, they may change without notice */
  33 #ifndef _KERNEL
  34 #error Only include this file in the kernel
  35 #endif
  36
  37 #include <machine/atomic.h>
  38 #include <machine/cpufunc.h>
  39 #include <machine/cpuinfo.h>
  40 #include <machine/sysreg.h>
  41
  42 /*
  43  * Some kernel modules (dtrace all for example) are compiled
  44  * unconditionally with -DSMP. Although it looks like a bug,
  45  * handle this case here and in #elif condition in ARM_SMP_UP macro.
  46  */
  47 #if __ARM_ARCH <= 6 && defined(SMP) && !defined(KLD_MODULE)
  48 #error SMP option is not supported on ARMv6
  49 #endif
  50
  51 #if __ARM_ARCH <= 6 && defined(SMP_ON_UP)
  52 #error SMP_ON_UP option is only supported on ARMv7+ CPUs
  53 #endif
  54
  55 #if !defined(SMP) && defined(SMP_ON_UP)
  56 #error SMP option must be defined for SMP_ON_UP option
  57 #endif
  58
  59 #define CPU_ASID_KERNEL 0
  60
  61 #if defined(SMP_ON_UP)
  62 #define ARM_SMP_UP(smp_code, up_code)                           \
  63 do {                                                            \
  64         if (cpuinfo.mp_ext != 0) {                              \
  65                 smp_code;                                       \
  66         } else {                                                \
  67                 up_code;                                        \
  68         }                                                       \
  69 } while (0)
  70 #elif defined(SMP) && __ARM_ARCH > 6
  71 #define ARM_SMP_UP(smp_code, up_code)                           \
  72 do {                                                            \
  73         smp_code;                                               \
  74 } while (0)
  75 #else
  76 #define ARM_SMP_UP(smp_code, up_code)                           \
  77 do {                                                            \
  78         up_code;                                                \
  79 } while (0)
  80 #endif
  81
  82 void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
  83 vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
  84 vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
  85
  86 #ifdef DEV_PMU
  87 #include <sys/pcpu.h>
  88 #define PMU_OVSR_C              0x80000000      /* Cycle Counter */
  89 extern uint32_t ccnt_hi[MAXCPU];
  90 extern int pmu_attched;
  91 #endif /* DEV_PMU */
  92
  93 #define sev()  __asm __volatile("sev" : : : "memory")
  94 #define wfe()  __asm __volatile("wfe" : : : "memory")
  95
  96 /*
  97  * Macros to generate CP15 (system control processor) read/write functions.
  98  */
  99 #define _FX(s...) #s
 100
 101 #define _RF0(fname, aname...)                                           \
 102 static __inline uint32_t                                                \
 103 fname(void)                                                             \
 104 {                                                                       \
 105         uint32_t reg;                                                   \
 106         __asm __volatile("mrc\t" _FX(aname): "=r" (reg));               \
 107         return(reg);                                                    \
 108 }
 109
 110 #define _R64F0(fname, aname)                                            \
 111 static __inline uint64_t                                                \
 112 fname(void)                                                             \
 113 {                                                                       \
 114         uint64_t reg;                                                   \
 115         __asm __volatile("mrrc\t" _FX(aname): "=r" (reg));              \
 116         return(reg);                                                    \
 117 }
 118
 119 #define _WF0(fname, aname...)                                           \
 120 static __inline void                                                    \
 121 fname(void)                                                             \
 122 {                                                                       \
 123         __asm __volatile("mcr\t" _FX(aname));                           \
 124 }
 125
 126 #define _WF1(fname, aname...)                                           \
 127 static __inline void                                                    \
 128 fname(uint32_t reg)                                                     \
 129 {                                                                       \
 130         __asm __volatile("mcr\t" _FX(aname):: "r" (reg));               \
 131 }
 132
 133 #define _W64F1(fname, aname...)                                         \
 134 static __inline void                                                    \
 135 fname(uint64_t reg)                                                     \
 136 {                                                                       \
 137         __asm __volatile("mcrr\t" _FX(aname):: "r" (reg));              \
 138 }
 139
 140 /*
 141  * Raw CP15  maintenance operations
 142  * !!! not for external use !!!
 143  */
 144
 145 /* TLB */
 146
 147 _WF0(_CP15_TLBIALL, CP15_TLBIALL)               /* Invalidate entire unified TLB */
 148 #if __ARM_ARCH >= 7 && defined(SMP)
 149 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)           /* Invalidate entire unified TLB IS */
 150 #endif
 151 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))         /* Invalidate unified TLB by ASID */
 152 #if __ARM_ARCH >= 7 && defined(SMP)
 153 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))     /* Invalidate unified TLB by ASID IS */
 154 #endif
 155 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))         /* Invalidate unified TLB by MVA, all ASID */
 156 #if __ARM_ARCH >= 7 && defined(SMP)
 157 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))     /* Invalidate unified TLB by MVA, all ASID IS */
 158 #endif
 159 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))           /* Invalidate unified TLB by MVA */
 160
 161 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
 162
 163 /* Cache and Branch predictor */
 164
 165 _WF0(_CP15_BPIALL, CP15_BPIALL)                 /* Branch predictor invalidate all */
 166 #if __ARM_ARCH >= 7 && defined(SMP)
 167 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS)             /* Branch predictor invalidate all IS */
 168 #endif
 169 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))             /* Branch predictor invalidate by MVA */
 170 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0))         /* Data cache clean and invalidate by MVA PoC */
 171 _WF1(_CP15_DCCISW, CP15_DCCISW(%0))             /* Data cache clean and invalidate by set/way */
 172 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0))           /* Data cache clean by MVA PoC */
 173 #if __ARM_ARCH >= 7
 174 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0))           /* Data cache clean by MVA PoU */
 175 #endif
 176 _WF1(_CP15_DCCSW, CP15_DCCSW(%0))               /* Data cache clean by set/way */
 177 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))           /* Data cache invalidate by MVA PoC */
 178 _WF1(_CP15_DCISW, CP15_DCISW(%0))               /* Data cache invalidate by set/way */
 179 _WF0(_CP15_ICIALLU, CP15_ICIALLU)               /* Instruction cache invalidate all PoU */
 180 #if __ARM_ARCH >= 7 && defined(SMP)
 181 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS)           /* Instruction cache invalidate all PoU IS */
 182 #endif
 183 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))           /* Instruction cache invalidate */
 184
 185 /*
 186  * Publicly accessible functions
 187  */
 188
 189 /* CP14 Debug Registers */
 190 _RF0(cp14_dbgdidr_get, CP14_DBGDIDR(%0))
 191 _RF0(cp14_dbgprsr_get, CP14_DBGPRSR(%0))
 192 _RF0(cp14_dbgoslsr_get, CP14_DBGOSLSR(%0))
 193 _RF0(cp14_dbgosdlr_get, CP14_DBGOSDLR(%0))
 194 _RF0(cp14_dbgdscrint_get, CP14_DBGDSCRint(%0))
 195
 196 _WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0))
 197 _WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0))
 198 _WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0))
 199 _WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0))
 200
 201 /* Various control registers */
 202
 203 _RF0(cp15_cpacr_get, CP15_CPACR(%0))
 204 _WF1(cp15_cpacr_set, CP15_CPACR(%0))
 205 _RF0(cp15_dfsr_get, CP15_DFSR(%0))
 206 _RF0(cp15_ifsr_get, CP15_IFSR(%0))
 207 _WF1(cp15_prrr_set, CP15_PRRR(%0))
 208 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
 209 _RF0(cp15_ttbr_get, CP15_TTBR0(%0))
 210 _RF0(cp15_dfar_get, CP15_DFAR(%0))
 211 #if __ARM_ARCH >= 7
 212 _RF0(cp15_ifar_get, CP15_IFAR(%0))
 213 _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
 214 #endif
 215 _RF0(cp15_actlr_get, CP15_ACTLR(%0))
 216 _WF1(cp15_actlr_set, CP15_ACTLR(%0))
 217 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
 218 _WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
 219 _WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0))
 220 _WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0))
 221 _RF0(cp15_par_get, CP15_PAR(%0))
 222 _RF0(cp15_sctlr_get, CP15_SCTLR(%0))
 223
 224 /*CPU id registers */
 225 _RF0(cp15_midr_get, CP15_MIDR(%0))
 226 _RF0(cp15_ctr_get, CP15_CTR(%0))
 227 _RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
 228 _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
 229 _RF0(cp15_mpidr_get, CP15_MPIDR(%0))
 230 _RF0(cp15_revidr_get, CP15_REVIDR(%0))
 231 _RF0(cp15_ccsidr_get, CP15_CCSIDR(%0))
 232 _RF0(cp15_clidr_get, CP15_CLIDR(%0))
 233 _RF0(cp15_aidr_get, CP15_AIDR(%0))
 234 _WF1(cp15_csselr_set, CP15_CSSELR(%0))
 235 _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
 236 _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
 237 _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
 238 _RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
 239 _RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
 240 _RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
 241 _RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
 242 _RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
 243 _RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
 244 _RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
 245 _RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
 246 _RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
 247 _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
 248 _RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
 249 _RF0(cp15_cbar_get, CP15_CBAR(%0))
 250
 251 /* Performance Monitor registers */
 252
 253 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
 254 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 255 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 256 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 257 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 258 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 259 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 260 #elif __ARM_ARCH > 6
 261 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 262 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 263 _RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
 264 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
 265 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
 266 _RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
 267 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
 268 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
 269 _RF0(cp15_pmselr_get, CP15_PMSELR(%0))
 270 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
 271 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 272 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 273 _RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
 274 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
 275 _RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
 276 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
 277 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 278 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 279 _RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
 280 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
 281 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
 282 #endif
 283
 284 _RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
 285 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
 286 _RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
 287 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
 288 _RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
 289 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
 290
 291 /* Generic Timer registers - only use when you know the hardware is available */
 292 _RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
 293 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
 294 _RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
 295 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
 296 _RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
 297 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
 298 _RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
 299 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
 300 _RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
 301 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
 302 _RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
 303 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
 304 _RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
 305 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
 306 _RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
 307 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
 308 _RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
 309 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
 310
 311 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
 312 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
 313 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
 314 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
 315 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
 316 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
 317 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
 318 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
 319 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
 320 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
 321
 322 #undef  _FX
 323 #undef  _RF0
 324 #undef  _WF0
 325 #undef  _WF1
 326
 327 /*
 328  * TLB maintenance operations.
 329  */
 330
 331 /* Local (i.e. not broadcasting ) operations.  */
 332
 333 /* Flush all TLB entries (even global). */
 334 static __inline void
 335 tlb_flush_all_local(void)
 336 {
 337
 338         dsb();
 339         _CP15_TLBIALL();
 340         dsb();
 341 }
 342
 343 /* Flush all not global TLB entries. */
 344 static __inline void
 345 tlb_flush_all_ng_local(void)
 346 {
 347
 348         dsb();
 349         _CP15_TLBIASID(CPU_ASID_KERNEL);
 350         dsb();
 351 }
 352
 353 /* Flush single TLB entry (even global). */
 354 static __inline void
 355 tlb_flush_local(vm_offset_t va)
 356 {
 357
 358         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 359
 360         dsb();
 361         _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 362         dsb();
 363 }
 364
 365 /* Flush range of TLB entries (even global). */
 366 static __inline void
 367 tlb_flush_range_local(vm_offset_t va, vm_size_t size)
 368 {
 369         vm_offset_t eva = va + size;
 370
 371         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 372         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 373             size));
 374
 375         dsb();
 376         for (; va < eva; va += PAGE_SIZE)
 377                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 378         dsb();
 379 }
 380
 381 /* Broadcasting operations. */
 382 #if __ARM_ARCH >= 7 && defined(SMP)
 383
 384 static __inline void
 385 tlb_flush_all(void)
 386 {
 387
 388         dsb();
 389         ARM_SMP_UP(
 390             _CP15_TLBIALLIS(),
 391             _CP15_TLBIALL()
 392         );
 393         dsb();
 394 }
 395
 396 static __inline void
 397 tlb_flush_all_ng(void)
 398 {
 399
 400         dsb();
 401         ARM_SMP_UP(
 402             _CP15_TLBIASIDIS(CPU_ASID_KERNEL),
 403             _CP15_TLBIASID(CPU_ASID_KERNEL)
 404         );
 405         dsb();
 406 }
 407
 408 static __inline void
 409 tlb_flush(vm_offset_t va)
 410 {
 411
 412         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 413
 414         dsb();
 415         ARM_SMP_UP(
 416             _CP15_TLBIMVAAIS(va),
 417             _CP15_TLBIMVA(va | CPU_ASID_KERNEL)
 418         );
 419         dsb();
 420 }
 421
 422 static __inline void
 423 tlb_flush_range(vm_offset_t va,  vm_size_t size)
 424 {
 425         vm_offset_t eva = va + size;
 426
 427         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 428         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 429             size));
 430
 431         dsb();
 432         ARM_SMP_UP(
 433                 {
 434                         for (; va < eva; va += PAGE_SIZE)
 435                                 _CP15_TLBIMVAAIS(va);
 436                 },
 437                 {
 438                         for (; va < eva; va += PAGE_SIZE)
 439                                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 440                 }
 441         );
 442         dsb();
 443 }
 444 #else /* __ARM_ARCH < 7 */
 445
 446 #define tlb_flush_all()                 tlb_flush_all_local()
 447 #define tlb_flush_all_ng()              tlb_flush_all_ng_local()
 448 #define tlb_flush(va)                   tlb_flush_local(va)
 449 #define tlb_flush_range(va, size)       tlb_flush_range_local(va, size)
 450
 451 #endif /* __ARM_ARCH < 7 */
 452
 453 /*
 454  * Cache maintenance operations.
 455  */
 456
 457 /*  Sync I and D caches to PoU */
 458 static __inline void
 459 icache_sync(vm_offset_t va, vm_size_t size)
 460 {
 461         vm_offset_t eva = va + size;
 462
 463         dsb();
 464         va &= ~cpuinfo.dcache_line_mask;
 465
 466         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 467 #if __ARM_ARCH >= 7
 468                 _CP15_DCCMVAU(va);
 469 #else
 470                 _CP15_DCCMVAC(va);
 471 #endif
 472         }
 473         dsb();
 474         ARM_SMP_UP(
 475                         _CP15_ICIALLUIS(),
 476                         _CP15_ICIALLU()
 477         );
 478         dsb();
 479         isb();
 480 }
 481
 482 /*  Invalidate I cache */
 483 static __inline void
 484 icache_inv_all(void)
 485 {
 486
 487         ARM_SMP_UP(
 488                 _CP15_ICIALLUIS(),
 489                 _CP15_ICIALLU()
 490         );
 491         dsb();
 492         isb();
 493 }
 494
 495 /* Invalidate branch predictor buffer */
 496 static __inline void
 497 bpb_inv_all(void)
 498 {
 499
 500         ARM_SMP_UP(
 501                 _CP15_BPIALLIS(),
 502                 _CP15_BPIALL()
 503         );
 504         dsb();
 505         isb();
 506 }
 507
 508 /* Write back D-cache to PoU */
 509 static __inline void
 510 dcache_wb_pou(vm_offset_t va, vm_size_t size)
 511 {
 512         vm_offset_t eva = va + size;
 513
 514         dsb();
 515         va &= ~cpuinfo.dcache_line_mask;
 516         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 517 #if __ARM_ARCH >= 7
 518                 _CP15_DCCMVAU(va);
 519 #else
 520                 _CP15_DCCMVAC(va);
 521 #endif
 522         }
 523         dsb();
 524 }
 525
 526 /*
 527  * Invalidate D-cache to PoC
 528  *
 529  * Caches are invalidated from outermost to innermost as fresh cachelines
 530  * flow in this direction. In given range, if there was no dirty cacheline
 531  * in any cache before, no stale cacheline should remain in them after this
 532  * operation finishes.
 533  */
 534 static __inline void
 535 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 536 {
 537         vm_offset_t eva = va + size;
 538
 539         dsb();
 540         /* invalidate L2 first */
 541         cpu_l2cache_inv_range(pa, size);
 542
 543         /* then L1 */
 544         va &= ~cpuinfo.dcache_line_mask;
 545         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 546                 _CP15_DCIMVAC(va);
 547         }
 548         dsb();
 549 }
 550
 551 /*
 552  * Discard D-cache lines to PoC, prior to overwrite by DMA engine.
 553  *
 554  * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't
 555  * flow into L1 while invalidating.  This routine is intended to be used only
 556  * when invalidating a buffer before a DMA operation loads new data into memory.
 557  * The concern in this case is that dirty lines are not evicted to main memory,
 558  * overwriting the DMA data.  For that reason, the L1 is done first to ensure
 559  * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned.
 560  */
 561 static __inline void
 562 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 563 {
 564         vm_offset_t eva = va + size;
 565
 566         /* invalidate L1 first */
 567         dsb();
 568         va &= ~cpuinfo.dcache_line_mask;
 569         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 570                 _CP15_DCIMVAC(va);
 571         }
 572         dsb();
 573
 574         /* then L2 */
 575         cpu_l2cache_inv_range(pa, size);
 576 }
 577
 578 /*
 579  * Write back D-cache to PoC
 580  *
 581  * Caches are written back from innermost to outermost as dirty cachelines
 582  * flow in this direction. In given range, no dirty cacheline should remain
 583  * in any cache after this operation finishes.
 584  */
 585 static __inline void
 586 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 587 {
 588         vm_offset_t eva = va + size;
 589
 590         dsb();
 591         va &= ~cpuinfo.dcache_line_mask;
 592         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 593                 _CP15_DCCMVAC(va);
 594         }
 595         dsb();
 596
 597         cpu_l2cache_wb_range(pa, size);
 598 }
 599
 600 /* Write back and invalidate D-cache to PoC */
 601 static __inline void
 602 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 603 {
 604         vm_offset_t va;
 605         vm_offset_t eva = sva + size;
 606
 607         dsb();
 608         /* write back L1 first */
 609         va = sva & ~cpuinfo.dcache_line_mask;
 610         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 611                 _CP15_DCCMVAC(va);
 612         }
 613         dsb();
 614
 615         /* then write back and invalidate L2 */
 616         cpu_l2cache_wbinv_range(pa, size);
 617
 618         /* then invalidate L1 */
 619         va = sva & ~cpuinfo.dcache_line_mask;
 620         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 621                 _CP15_DCIMVAC(va);
 622         }
 623         dsb();
 624 }
 625
 626 /* Set TTB0 register */
 627 static __inline void
 628 cp15_ttbr_set(uint32_t reg)
 629 {
 630         dsb();
 631         _CP15_TTB_SET(reg);
 632         dsb();
 633         _CP15_BPIALL();
 634         dsb();
 635         isb();
 636         tlb_flush_all_ng_local();
 637 }
 638
 639 /*
 640  * Functions for address checking:
 641  *
 642  *  cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access
 643  *  cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access
 644  *  cp15_ats1cur_check() ... check stage 1 unprivileged (PL0) read access
 645  *  cp15_ats1cuw_check() ... check stage 1 unprivileged (PL0) write access
 646  *
 647  * They must be called while interrupts are disabled to get consistent result.
 648  */
 649 static __inline int
 650 cp15_ats1cpr_check(vm_offset_t addr)
 651 {
 652
 653         cp15_ats1cpr_set(addr);
 654         isb();
 655         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 656 }
 657
 658 static __inline int
 659 cp15_ats1cpw_check(vm_offset_t addr)
 660 {
 661
 662         cp15_ats1cpw_set(addr);
 663         isb();
 664         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 665 }
 666
 667 static __inline int
 668 cp15_ats1cur_check(vm_offset_t addr)
 669 {
 670
 671         cp15_ats1cur_set(addr);
 672         isb();
 673         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 674 }
 675
 676 static __inline int
 677 cp15_ats1cuw_check(vm_offset_t addr)
 678 {
 679
 680         cp15_ats1cuw_set(addr);
 681         isb();
 682         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 683 }
 684
 685 #endif /* !MACHINE_CPU_V6_H */