sys/arm/include/cpu-v6.h

   1 /*-
   2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
   3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 #ifndef MACHINE_CPU_V6_H
  30 #define MACHINE_CPU_V6_H
  31
  32 /* There are no user serviceable parts here, they may change without notice */
  33 #ifndef _KERNEL
  34 #error Only include this file in the kernel
  35 #else
  36
  37 #include <machine/acle-compat.h>
  38 #include "machine/atomic.h"
  39 #include "machine/cpufunc.h"
  40 #include "machine/cpuinfo.h"
  41 #include "machine/sysreg.h"
  42
  43 #define CPU_ASID_KERNEL 0
  44
  45 vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
  46 vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
  47
  48 /*
  49  * Macros to generate CP15 (system control processor) read/write functions.
  50  */
  51 #define _FX(s...) #s
  52
  53 #define _RF0(fname, aname...)                                           \
  54 static __inline register_t                                              \
  55 fname(void)                                                             \
  56 {                                                                       \
  57         register_t reg;                                                 \
  58         __asm __volatile("mrc\t" _FX(aname): "=r" (reg));               \
  59         return(reg);                                                    \
  60 }
  61
  62 #define _R64F0(fname, aname)                                            \
  63 static __inline uint64_t                                                \
  64 fname(void)                                                             \
  65 {                                                                       \
  66         uint64_t reg;                                                   \
  67         __asm __volatile("mrrc\t" _FX(aname): "=r" (reg));              \
  68         return(reg);                                                    \
  69 }
  70
  71 #define _WF0(fname, aname...)                                           \
  72 static __inline void                                                    \
  73 fname(void)                                                             \
  74 {                                                                       \
  75         __asm __volatile("mcr\t" _FX(aname));                           \
  76 }
  77
  78 #define _WF1(fname, aname...)                                           \
  79 static __inline void                                                    \
  80 fname(register_t reg)                                                   \
  81 {                                                                       \
  82         __asm __volatile("mcr\t" _FX(aname):: "r" (reg));               \
  83 }
  84
  85 #define _W64F1(fname, aname...)                                         \
  86 static __inline void                                                    \
  87 fname(uint64_t reg)                                                     \
  88 {                                                                       \
  89         __asm __volatile("mcrr\t" _FX(aname):: "r" (reg));              \
  90 }
  91
  92 /*
  93  * Raw CP15  maintenance operations
  94  * !!! not for external use !!!
  95  */
  96
  97 /* TLB */
  98
  99 _WF0(_CP15_TLBIALL, CP15_TLBIALL)               /* Invalidate entire unified TLB */
 100 #if __ARM_ARCH >= 7 && defined SMP
 101 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)           /* Invalidate entire unified TLB IS */
 102 #endif
 103 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))         /* Invalidate unified TLB by ASID */
 104 #if __ARM_ARCH >= 7 && defined SMP
 105 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))     /* Invalidate unified TLB by ASID IS */
 106 #endif
 107 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))         /* Invalidate unified TLB by MVA, all ASID */
 108 #if __ARM_ARCH >= 7 && defined SMP
 109 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))     /* Invalidate unified TLB by MVA, all ASID IS */
 110 #endif
 111 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))           /* Invalidate unified TLB by MVA */
 112
 113 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
 114
 115 /* Cache and Branch predictor */
 116
 117 _WF0(_CP15_BPIALL, CP15_BPIALL)                 /* Branch predictor invalidate all */
 118 #if __ARM_ARCH >= 7 && defined SMP
 119 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS)             /* Branch predictor invalidate all IS */
 120 #endif
 121 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))             /* Branch predictor invalidate by MVA */
 122 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0))         /* Data cache clean and invalidate by MVA PoC */
 123 _WF1(_CP15_DCCISW, CP15_DCCISW(%0))             /* Data cache clean and invalidate by set/way */
 124 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0))           /* Data cache clean by MVA PoC */
 125 #if __ARM_ARCH >= 7
 126 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0))           /* Data cache clean by MVA PoU */
 127 #endif
 128 _WF1(_CP15_DCCSW, CP15_DCCSW(%0))               /* Data cache clean by set/way */
 129 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))           /* Data cache invalidate by MVA PoC */
 130 _WF1(_CP15_DCISW, CP15_DCISW(%0))               /* Data cache invalidate by set/way */
 131 _WF0(_CP15_ICIALLU, CP15_ICIALLU)               /* Instruction cache invalidate all PoU */
 132 #if __ARM_ARCH >= 7 && defined SMP
 133 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS)           /* Instruction cache invalidate all PoU IS */
 134 #endif
 135 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))           /* Instruction cache invalidate */
 136
 137 /*
 138  * Publicly accessible functions
 139  */
 140
 141 /* Various control registers */
 142
 143 _RF0(cp15_cpacr_get, CP15_CPACR(%0))
 144 _WF1(cp15_cpacr_set, CP15_CPACR(%0))
 145 _RF0(cp15_dfsr_get, CP15_DFSR(%0))
 146 _RF0(cp15_ifsr_get, CP15_IFSR(%0))
 147 _WF1(cp15_prrr_set, CP15_PRRR(%0))
 148 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
 149 _RF0(cp15_ttbr_get, CP15_TTBR0(%0))
 150 _RF0(cp15_dfar_get, CP15_DFAR(%0))
 151 #if __ARM_ARCH >= 7
 152 _RF0(cp15_ifar_get, CP15_IFAR(%0))
 153 _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
 154 #endif
 155 /* ARMv6+ and XScale */
 156 _RF0(cp15_actlr_get, CP15_ACTLR(%0))
 157 _WF1(cp15_actlr_set, CP15_ACTLR(%0))
 158 #if __ARM_ARCH >= 6
 159 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
 160 _WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
 161 _RF0(cp15_par_get, CP15_PAR(%0))
 162 _RF0(cp15_sctlr_get, CP15_SCTLR(%0))
 163 #endif
 164
 165 /*CPU id registers */
 166 _RF0(cp15_midr_get, CP15_MIDR(%0))
 167 _RF0(cp15_ctr_get, CP15_CTR(%0))
 168 _RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
 169 _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
 170 _RF0(cp15_mpidr_get, CP15_MPIDR(%0))
 171 _RF0(cp15_revidr_get, CP15_REVIDR(%0))
 172 _RF0(cp15_ccsidr_get, CP15_CCSIDR(%0))
 173 _RF0(cp15_clidr_get, CP15_CLIDR(%0))
 174 _RF0(cp15_aidr_get, CP15_AIDR(%0))
 175 _WF1(cp15_csselr_set, CP15_CSSELR(%0))
 176 _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
 177 _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
 178 _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
 179 _RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
 180 _RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
 181 _RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
 182 _RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
 183 _RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
 184 _RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
 185 _RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
 186 _RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
 187 _RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
 188 _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
 189 _RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
 190 _RF0(cp15_cbar_get, CP15_CBAR(%0))
 191
 192 /* Performance Monitor registers */
 193
 194 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
 195 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 196 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 197 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 198 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 199 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 200 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 201 #elif __ARM_ARCH > 6
 202 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 203 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 204 _RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
 205 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
 206 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
 207 _RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
 208 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
 209 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
 210 _RF0(cp15_pmselr_get, CP15_PMSELR(%0))
 211 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
 212 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 213 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 214 _RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
 215 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
 216 _RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
 217 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
 218 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 219 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 220 _RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
 221 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
 222 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
 223 #endif
 224
 225 _RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
 226 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
 227 _RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
 228 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
 229 _RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
 230 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
 231
 232 /* Generic Timer registers - only use when you know the hardware is available */
 233 _RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
 234 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
 235 _RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
 236 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
 237 _RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
 238 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
 239 _RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
 240 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
 241 _RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
 242 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
 243 _RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
 244 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
 245 _RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
 246 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
 247 _RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
 248 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
 249 _RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
 250 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
 251
 252 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
 253 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
 254 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
 255 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
 256 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
 257 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
 258 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
 259 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
 260 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
 261 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
 262
 263 #undef  _FX
 264 #undef  _RF0
 265 #undef  _WF0
 266 #undef  _WF1
 267
 268 #if __ARM_ARCH >= 6
 269 /*
 270  * Cache and TLB maintenance operations for armv6+ code.  The #else block
 271  * provides armv4/v5 implementations for a few of these used in common code.
 272  */
 273
 274 /*
 275  * TLB maintenance operations.
 276  */
 277
 278 /* Local (i.e. not broadcasting ) operations.  */
 279
 280 /* Flush all TLB entries (even global). */
 281 static __inline void
 282 tlb_flush_all_local(void)
 283 {
 284
 285         dsb();
 286         _CP15_TLBIALL();
 287         dsb();
 288 }
 289
 290 /* Flush all not global TLB entries. */
 291 static __inline void
 292 tlb_flush_all_ng_local(void)
 293 {
 294
 295         dsb();
 296         _CP15_TLBIASID(CPU_ASID_KERNEL);
 297         dsb();
 298 }
 299
 300 /* Flush single TLB entry (even global). */
 301 static __inline void
 302 tlb_flush_local(vm_offset_t va)
 303 {
 304
 305         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 306
 307         dsb();
 308         _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 309         dsb();
 310 }
 311
 312 /* Flush range of TLB entries (even global). */
 313 static __inline void
 314 tlb_flush_range_local(vm_offset_t va, vm_size_t size)
 315 {
 316         vm_offset_t eva = va + size;
 317
 318         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 319         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 320             size));
 321
 322         dsb();
 323         for (; va < eva; va += PAGE_SIZE)
 324                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 325         dsb();
 326 }
 327
 328 /* Broadcasting operations. */
 329 #if __ARM_ARCH >= 7 && defined SMP
 330
 331 static __inline void
 332 tlb_flush_all(void)
 333 {
 334
 335         dsb();
 336         _CP15_TLBIALLIS();
 337         dsb();
 338 }
 339
 340 static __inline void
 341 tlb_flush_all_ng(void)
 342 {
 343
 344         dsb();
 345         _CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 346         dsb();
 347 }
 348
 349 static __inline void
 350 tlb_flush(vm_offset_t va)
 351 {
 352
 353         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 354
 355         dsb();
 356         _CP15_TLBIMVAAIS(va);
 357         dsb();
 358 }
 359
 360 static __inline void
 361 tlb_flush_range(vm_offset_t va,  vm_size_t size)
 362 {
 363         vm_offset_t eva = va + size;
 364
 365         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 366         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 367             size));
 368
 369         dsb();
 370         for (; va < eva; va += PAGE_SIZE)
 371                 _CP15_TLBIMVAAIS(va);
 372         dsb();
 373 }
 374 #else /* SMP */
 375
 376 #define tlb_flush_all()                 tlb_flush_all_local()
 377 #define tlb_flush_all_ng()              tlb_flush_all_ng_local()
 378 #define tlb_flush(va)                   tlb_flush_local(va)
 379 #define tlb_flush_range(va, size)       tlb_flush_range_local(va, size)
 380
 381 #endif /* SMP */
 382
 383 /*
 384  * Cache maintenance operations.
 385  */
 386
 387 /*  Sync I and D caches to PoU */
 388 static __inline void
 389 icache_sync(vm_offset_t va, vm_size_t size)
 390 {
 391         vm_offset_t eva = va + size;
 392
 393         dsb();
 394         va &= ~cpuinfo.dcache_line_mask;
 395         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 396 #if __ARM_ARCH >= 7 && defined SMP
 397                 _CP15_DCCMVAU(va);
 398 #else
 399                 _CP15_DCCMVAC(va);
 400 #endif
 401         }
 402         dsb();
 403 #if __ARM_ARCH >= 7 && defined SMP
 404         _CP15_ICIALLUIS();
 405 #else
 406         _CP15_ICIALLU();
 407 #endif
 408         dsb();
 409         isb();
 410 }
 411
 412 /*  Invalidate I cache */
 413 static __inline void
 414 icache_inv_all(void)
 415 {
 416 #if __ARM_ARCH >= 7 && defined SMP
 417         _CP15_ICIALLUIS();
 418 #else
 419         _CP15_ICIALLU();
 420 #endif
 421         dsb();
 422         isb();
 423 }
 424
 425 /* Invalidate branch predictor buffer */
 426 static __inline void
 427 bpb_inv_all(void)
 428 {
 429 #if __ARM_ARCH >= 7 && defined SMP
 430         _CP15_BPIALLIS();
 431 #else
 432         _CP15_BPIALL();
 433 #endif
 434         dsb();
 435         isb();
 436 }
 437
 438 /* Write back D-cache to PoU */
 439 static __inline void
 440 dcache_wb_pou(vm_offset_t va, vm_size_t size)
 441 {
 442         vm_offset_t eva = va + size;
 443
 444         dsb();
 445         va &= ~cpuinfo.dcache_line_mask;
 446         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 447 #if __ARM_ARCH >= 7 && defined SMP
 448                 _CP15_DCCMVAU(va);
 449 #else
 450                 _CP15_DCCMVAC(va);
 451 #endif
 452         }
 453         dsb();
 454 }
 455
 456 /*
 457  * Invalidate D-cache to PoC
 458  *
 459  * Caches are invalidated from outermost to innermost as fresh cachelines
 460  * flow in this direction. In given range, if there was no dirty cacheline
 461  * in any cache before, no stale cacheline should remain in them after this
 462  * operation finishes.
 463  */
 464 static __inline void
 465 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 466 {
 467         vm_offset_t eva = va + size;
 468
 469         dsb();
 470         /* invalidate L2 first */
 471         cpu_l2cache_inv_range(pa, size);
 472
 473         /* then L1 */
 474         va &= ~cpuinfo.dcache_line_mask;
 475         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 476                 _CP15_DCIMVAC(va);
 477         }
 478         dsb();
 479 }
 480
 481 /*
 482  * Discard D-cache lines to PoC, prior to overwrite by DMA engine.
 483  *
 484  * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't
 485  * flow into L1 while invalidating.  This routine is intended to be used only
 486  * when invalidating a buffer before a DMA operation loads new data into memory.
 487  * The concern in this case is that dirty lines are not evicted to main memory,
 488  * overwriting the DMA data.  For that reason, the L1 is done first to ensure
 489  * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned.
 490  */
 491 static __inline void
 492 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 493 {
 494         vm_offset_t eva = va + size;
 495
 496         /* invalidate L1 first */
 497         dsb();
 498         va &= ~cpuinfo.dcache_line_mask;
 499         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 500                 _CP15_DCIMVAC(va);
 501         }
 502         dsb();
 503
 504         /* then L2 */
 505         cpu_l2cache_inv_range(pa, size);
 506 }
 507
 508 /*
 509  * Write back D-cache to PoC
 510  *
 511  * Caches are written back from innermost to outermost as dirty cachelines
 512  * flow in this direction. In given range, no dirty cacheline should remain
 513  * in any cache after this operation finishes.
 514  */
 515 static __inline void
 516 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 517 {
 518         vm_offset_t eva = va + size;
 519
 520         dsb();
 521         va &= ~cpuinfo.dcache_line_mask;
 522         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 523                 _CP15_DCCMVAC(va);
 524         }
 525         dsb();
 526
 527         cpu_l2cache_wb_range(pa, size);
 528 }
 529
 530 /* Write back and invalidate D-cache to PoC */
 531 static __inline void
 532 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 533 {
 534         vm_offset_t va;
 535         vm_offset_t eva = sva + size;
 536
 537         dsb();
 538         /* write back L1 first */
 539         va = sva & ~cpuinfo.dcache_line_mask;
 540         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 541                 _CP15_DCCMVAC(va);
 542         }
 543         dsb();
 544
 545         /* then write back and invalidate L2 */
 546         cpu_l2cache_wbinv_range(pa, size);
 547
 548         /* then invalidate L1 */
 549         va = sva & ~cpuinfo.dcache_line_mask;
 550         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 551                 _CP15_DCIMVAC(va);
 552         }
 553         dsb();
 554 }
 555
 556 /* Set TTB0 register */
 557 static __inline void
 558 cp15_ttbr_set(uint32_t reg)
 559 {
 560         dsb();
 561         _CP15_TTB_SET(reg);
 562         dsb();
 563         _CP15_BPIALL();
 564         dsb();
 565         isb();
 566         tlb_flush_all_ng_local();
 567 }
 568
 569 #else /* ! __ARM_ARCH >= 6 */
 570
 571 /*
 572  * armv4/5 compatibility shims.
 573  *
 574  * These functions provide armv4 cache maintenance using the new armv6 names.
 575  * Included here are just the functions actually used now in common code; it may
 576  * be necessary to add things here over time.
 577  *
 578  * The callers of the dcache functions expect these routines to handle address
 579  * and size values which are not aligned to cacheline boundaries; the armv4 and
 580  * armv5 asm code handles that.
 581  */
 582
 583 static __inline void
 584 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 585 {
 586
 587         cpu_dcache_inv_range(va, size);
 588         cpu_l2cache_inv_range(va, size);
 589 }
 590
 591 static __inline void
 592 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 593 {
 594
 595         /* See armv6 code, above, for why we do L2 before L1 in this case. */
 596         cpu_l2cache_inv_range(va, size);
 597         cpu_dcache_inv_range(va, size);
 598 }
 599
 600 static __inline void
 601 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 602 {
 603
 604         cpu_dcache_wb_range(va, size);
 605         cpu_l2cache_wb_range(va, size);
 606 }
 607
 608 #endif /* __ARM_ARCH >= 6 */
 609
 610 #endif /* _KERNEL */
 611
 612 #endif /* !MACHINE_CPU_V6_H */