sys/arm/include/cpu-v6.h

   1 /*-
   2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
   3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 #ifndef MACHINE_CPU_V6_H
  30 #define MACHINE_CPU_V6_H
  31
  32 /* There are no user serviceable parts here, they may change without notice */
  33 #ifndef _KERNEL
  34 #error Only include this file in the kernel
  35 #endif
  36
  37 #include <machine/atomic.h>
  38 #include <machine/cpufunc.h>
  39 #include <machine/cpuinfo.h>
  40 #include <machine/sysreg.h>
  41
  42 #if __ARM_ARCH < 6
  43 #error Only include this file for ARMv6
  44 #else
  45
  46 #define CPU_ASID_KERNEL 0
  47
  48 void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
  49 vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
  50 vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
  51
  52 #ifdef DEV_PMU
  53 #include <sys/pcpu.h>
  54 #define PMU_OVSR_C              0x80000000      /* Cycle Counter */
  55 extern uint32_t ccnt_hi[MAXCPU];
  56 extern int pmu_attched;
  57 #endif /* DEV_PMU */
  58
  59
  60 /*
  61  * Macros to generate CP15 (system control processor) read/write functions.
  62  */
  63 #define _FX(s...) #s
  64
  65 #define _RF0(fname, aname...)                                           \
  66 static __inline register_t                                              \
  67 fname(void)                                                             \
  68 {                                                                       \
  69         register_t reg;                                                 \
  70         __asm __volatile("mrc\t" _FX(aname): "=r" (reg));               \
  71         return(reg);                                                    \
  72 }
  73
  74 #define _R64F0(fname, aname)                                            \
  75 static __inline uint64_t                                                \
  76 fname(void)                                                             \
  77 {                                                                       \
  78         uint64_t reg;                                                   \
  79         __asm __volatile("mrrc\t" _FX(aname): "=r" (reg));              \
  80         return(reg);                                                    \
  81 }
  82
  83 #define _WF0(fname, aname...)                                           \
  84 static __inline void                                                    \
  85 fname(void)                                                             \
  86 {                                                                       \
  87         __asm __volatile("mcr\t" _FX(aname));                           \
  88 }
  89
  90 #define _WF1(fname, aname...)                                           \
  91 static __inline void                                                    \
  92 fname(register_t reg)                                                   \
  93 {                                                                       \
  94         __asm __volatile("mcr\t" _FX(aname):: "r" (reg));               \
  95 }
  96
  97 #define _W64F1(fname, aname...)                                         \
  98 static __inline void                                                    \
  99 fname(uint64_t reg)                                                     \
 100 {                                                                       \
 101         __asm __volatile("mcrr\t" _FX(aname):: "r" (reg));              \
 102 }
 103
 104 /*
 105  * Raw CP15  maintenance operations
 106  * !!! not for external use !!!
 107  */
 108
 109 /* TLB */
 110
 111 _WF0(_CP15_TLBIALL, CP15_TLBIALL)               /* Invalidate entire unified TLB */
 112 #if __ARM_ARCH >= 7 && defined SMP
 113 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)           /* Invalidate entire unified TLB IS */
 114 #endif
 115 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))         /* Invalidate unified TLB by ASID */
 116 #if __ARM_ARCH >= 7 && defined SMP
 117 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))     /* Invalidate unified TLB by ASID IS */
 118 #endif
 119 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))         /* Invalidate unified TLB by MVA, all ASID */
 120 #if __ARM_ARCH >= 7 && defined SMP
 121 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))     /* Invalidate unified TLB by MVA, all ASID IS */
 122 #endif
 123 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))           /* Invalidate unified TLB by MVA */
 124
 125 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
 126
 127 /* Cache and Branch predictor */
 128
 129 _WF0(_CP15_BPIALL, CP15_BPIALL)                 /* Branch predictor invalidate all */
 130 #if __ARM_ARCH >= 7 && defined SMP
 131 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS)             /* Branch predictor invalidate all IS */
 132 #endif
 133 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))             /* Branch predictor invalidate by MVA */
 134 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0))         /* Data cache clean and invalidate by MVA PoC */
 135 _WF1(_CP15_DCCISW, CP15_DCCISW(%0))             /* Data cache clean and invalidate by set/way */
 136 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0))           /* Data cache clean by MVA PoC */
 137 #if __ARM_ARCH >= 7
 138 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0))           /* Data cache clean by MVA PoU */
 139 #endif
 140 _WF1(_CP15_DCCSW, CP15_DCCSW(%0))               /* Data cache clean by set/way */
 141 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))           /* Data cache invalidate by MVA PoC */
 142 _WF1(_CP15_DCISW, CP15_DCISW(%0))               /* Data cache invalidate by set/way */
 143 _WF0(_CP15_ICIALLU, CP15_ICIALLU)               /* Instruction cache invalidate all PoU */
 144 #if __ARM_ARCH >= 7 && defined SMP
 145 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS)           /* Instruction cache invalidate all PoU IS */
 146 #endif
 147 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))           /* Instruction cache invalidate */
 148
 149 /*
 150  * Publicly accessible functions
 151  */
 152
 153 /* CP14 Debug Registers */
 154 _RF0(cp14_dbgdidr_get, CP14_DBGDIDR(%0))
 155 _RF0(cp14_dbgprsr_get, CP14_DBGPRSR(%0))
 156 _RF0(cp14_dbgoslsr_get, CP14_DBGOSLSR(%0))
 157 _RF0(cp14_dbgosdlr_get, CP14_DBGOSDLR(%0))
 158 _RF0(cp14_dbgdscrint_get, CP14_DBGDSCRint(%0))
 159
 160 _WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0))
 161 _WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0))
 162 _WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0))
 163 _WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0))
 164
 165 /* Various control registers */
 166
 167 _RF0(cp15_cpacr_get, CP15_CPACR(%0))
 168 _WF1(cp15_cpacr_set, CP15_CPACR(%0))
 169 _RF0(cp15_dfsr_get, CP15_DFSR(%0))
 170 _RF0(cp15_ifsr_get, CP15_IFSR(%0))
 171 _WF1(cp15_prrr_set, CP15_PRRR(%0))
 172 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
 173 _RF0(cp15_ttbr_get, CP15_TTBR0(%0))
 174 _RF0(cp15_dfar_get, CP15_DFAR(%0))
 175 #if __ARM_ARCH >= 7
 176 _RF0(cp15_ifar_get, CP15_IFAR(%0))
 177 _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
 178 #endif
 179 _RF0(cp15_actlr_get, CP15_ACTLR(%0))
 180 _WF1(cp15_actlr_set, CP15_ACTLR(%0))
 181 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
 182 _WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
 183 _WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0))
 184 _WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0))
 185 _RF0(cp15_par_get, CP15_PAR(%0))
 186 _RF0(cp15_sctlr_get, CP15_SCTLR(%0))
 187
 188 /*CPU id registers */
 189 _RF0(cp15_midr_get, CP15_MIDR(%0))
 190 _RF0(cp15_ctr_get, CP15_CTR(%0))
 191 _RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
 192 _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
 193 _RF0(cp15_mpidr_get, CP15_MPIDR(%0))
 194 _RF0(cp15_revidr_get, CP15_REVIDR(%0))
 195 _RF0(cp15_ccsidr_get, CP15_CCSIDR(%0))
 196 _RF0(cp15_clidr_get, CP15_CLIDR(%0))
 197 _RF0(cp15_aidr_get, CP15_AIDR(%0))
 198 _WF1(cp15_csselr_set, CP15_CSSELR(%0))
 199 _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
 200 _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
 201 _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
 202 _RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
 203 _RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
 204 _RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
 205 _RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
 206 _RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
 207 _RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
 208 _RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
 209 _RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
 210 _RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
 211 _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
 212 _RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
 213 _RF0(cp15_cbar_get, CP15_CBAR(%0))
 214
 215 /* Performance Monitor registers */
 216
 217 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
 218 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 219 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 220 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 221 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 222 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 223 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 224 #elif __ARM_ARCH > 6
 225 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 226 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 227 _RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
 228 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
 229 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
 230 _RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
 231 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
 232 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
 233 _RF0(cp15_pmselr_get, CP15_PMSELR(%0))
 234 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
 235 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 236 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 237 _RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
 238 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
 239 _RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
 240 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
 241 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 242 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 243 _RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
 244 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
 245 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
 246 #endif
 247
 248 _RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
 249 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
 250 _RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
 251 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
 252 _RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
 253 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
 254
 255 /* Generic Timer registers - only use when you know the hardware is available */
 256 _RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
 257 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
 258 _RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
 259 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
 260 _RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
 261 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
 262 _RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
 263 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
 264 _RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
 265 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
 266 _RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
 267 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
 268 _RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
 269 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
 270 _RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
 271 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
 272 _RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
 273 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
 274
 275 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
 276 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
 277 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
 278 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
 279 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
 280 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
 281 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
 282 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
 283 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
 284 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
 285
 286 #undef  _FX
 287 #undef  _RF0
 288 #undef  _WF0
 289 #undef  _WF1
 290
 291 /*
 292  * TLB maintenance operations.
 293  */
 294
 295 /* Local (i.e. not broadcasting ) operations.  */
 296
 297 /* Flush all TLB entries (even global). */
 298 static __inline void
 299 tlb_flush_all_local(void)
 300 {
 301
 302         dsb();
 303         _CP15_TLBIALL();
 304         dsb();
 305 }
 306
 307 /* Flush all not global TLB entries. */
 308 static __inline void
 309 tlb_flush_all_ng_local(void)
 310 {
 311
 312         dsb();
 313         _CP15_TLBIASID(CPU_ASID_KERNEL);
 314         dsb();
 315 }
 316
 317 /* Flush single TLB entry (even global). */
 318 static __inline void
 319 tlb_flush_local(vm_offset_t va)
 320 {
 321
 322         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 323
 324         dsb();
 325         _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 326         dsb();
 327 }
 328
 329 /* Flush range of TLB entries (even global). */
 330 static __inline void
 331 tlb_flush_range_local(vm_offset_t va, vm_size_t size)
 332 {
 333         vm_offset_t eva = va + size;
 334
 335         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 336         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 337             size));
 338
 339         dsb();
 340         for (; va < eva; va += PAGE_SIZE)
 341                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 342         dsb();
 343 }
 344
 345 /* Broadcasting operations. */
 346 #if __ARM_ARCH >= 7 && defined SMP
 347
 348 /* Used to detect SMP */
 349 extern int mp_ncpus;
 350
 351 static __inline void
 352 tlb_flush_all(void)
 353 {
 354
 355         dsb();
 356         if (mp_ncpus == 1)
 357                 _CP15_TLBIALL();
 358         else
 359                 _CP15_TLBIALLIS();
 360         dsb();
 361 }
 362
 363 static __inline void
 364 tlb_flush_all_ng(void)
 365 {
 366
 367         dsb();
 368         if (mp_ncpus == 1)
 369                 _CP15_TLBIASID(CPU_ASID_KERNEL);
 370         else
 371                 _CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 372         dsb();
 373 }
 374
 375 static __inline void
 376 tlb_flush(vm_offset_t va)
 377 {
 378
 379         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 380
 381         dsb();
 382         if (mp_ncpus == 1)
 383                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 384         else
 385                 _CP15_TLBIMVAAIS(va);
 386         dsb();
 387 }
 388
 389 static __inline void
 390 tlb_flush_range(vm_offset_t va,  vm_size_t size)
 391 {
 392         vm_offset_t eva = va + size;
 393
 394         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 395         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 396             size));
 397
 398         dsb();
 399         if (mp_ncpus == 1) {
 400                 for (; va < eva; va += PAGE_SIZE)
 401                         _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 402         } else {
 403                 for (; va < eva; va += PAGE_SIZE)
 404                         _CP15_TLBIMVAAIS(va);
 405         }
 406         dsb();
 407 }
 408 #else /* SMP */
 409
 410 #define tlb_flush_all()                 tlb_flush_all_local()
 411 #define tlb_flush_all_ng()              tlb_flush_all_ng_local()
 412 #define tlb_flush(va)                   tlb_flush_local(va)
 413 #define tlb_flush_range(va, size)       tlb_flush_range_local(va, size)
 414
 415 #endif /* SMP */
 416
 417 /*
 418  * Cache maintenance operations.
 419  */
 420
 421 /*  Sync I and D caches to PoU */
 422 static __inline void
 423 icache_sync(vm_offset_t va, vm_size_t size)
 424 {
 425         vm_offset_t eva = va + size;
 426
 427         dsb();
 428         va &= ~cpuinfo.dcache_line_mask;
 429         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 430 #if __ARM_ARCH >= 7 && defined SMP
 431                 if (mp_ncpus > 1)
 432                         _CP15_DCCMVAU(va);
 433                 else
 434 #endif
 435                         _CP15_DCCMVAC(va);
 436         }
 437         dsb();
 438 #if __ARM_ARCH >= 7 && defined SMP
 439         if (mp_ncpus > 1)
 440                 _CP15_ICIALLUIS();
 441         else
 442 #endif
 443                 _CP15_ICIALLU();
 444         dsb();
 445         isb();
 446 }
 447
 448 /*  Invalidate I cache */
 449 static __inline void
 450 icache_inv_all(void)
 451 {
 452 #if __ARM_ARCH >= 7 && defined SMP
 453         if (mp_ncpus > 1)
 454                 _CP15_ICIALLUIS();
 455         else
 456 #endif
 457                 _CP15_ICIALLU();
 458         dsb();
 459         isb();
 460 }
 461
 462 /* Invalidate branch predictor buffer */
 463 static __inline void
 464 bpb_inv_all(void)
 465 {
 466 #if __ARM_ARCH >= 7 && defined SMP
 467         if (mp_ncpus > 1)
 468                 _CP15_BPIALLIS();
 469         else
 470 #endif
 471                 _CP15_BPIALL();
 472         dsb();
 473         isb();
 474 }
 475
 476 /* Write back D-cache to PoU */
 477 static __inline void
 478 dcache_wb_pou(vm_offset_t va, vm_size_t size)
 479 {
 480         vm_offset_t eva = va + size;
 481
 482         dsb();
 483         va &= ~cpuinfo.dcache_line_mask;
 484         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 485 #if __ARM_ARCH >= 7 && defined SMP
 486                 if (mp_ncpus > 1)
 487                         _CP15_DCCMVAU(va);
 488                 else
 489 #endif
 490                         _CP15_DCCMVAC(va);
 491         }
 492         dsb();
 493 }
 494
 495 /*
 496  * Invalidate D-cache to PoC
 497  *
 498  * Caches are invalidated from outermost to innermost as fresh cachelines
 499  * flow in this direction. In given range, if there was no dirty cacheline
 500  * in any cache before, no stale cacheline should remain in them after this
 501  * operation finishes.
 502  */
 503 static __inline void
 504 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 505 {
 506         vm_offset_t eva = va + size;
 507
 508         dsb();
 509         /* invalidate L2 first */
 510         cpu_l2cache_inv_range(pa, size);
 511
 512         /* then L1 */
 513         va &= ~cpuinfo.dcache_line_mask;
 514         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 515                 _CP15_DCIMVAC(va);
 516         }
 517         dsb();
 518 }
 519
 520 /*
 521  * Discard D-cache lines to PoC, prior to overwrite by DMA engine.
 522  *
 523  * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't
 524  * flow into L1 while invalidating.  This routine is intended to be used only
 525  * when invalidating a buffer before a DMA operation loads new data into memory.
 526  * The concern in this case is that dirty lines are not evicted to main memory,
 527  * overwriting the DMA data.  For that reason, the L1 is done first to ensure
 528  * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned.
 529  */
 530 static __inline void
 531 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 532 {
 533         vm_offset_t eva = va + size;
 534
 535         /* invalidate L1 first */
 536         dsb();
 537         va &= ~cpuinfo.dcache_line_mask;
 538         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 539                 _CP15_DCIMVAC(va);
 540         }
 541         dsb();
 542
 543         /* then L2 */
 544         cpu_l2cache_inv_range(pa, size);
 545 }
 546
 547 /*
 548  * Write back D-cache to PoC
 549  *
 550  * Caches are written back from innermost to outermost as dirty cachelines
 551  * flow in this direction. In given range, no dirty cacheline should remain
 552  * in any cache after this operation finishes.
 553  */
 554 static __inline void
 555 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 556 {
 557         vm_offset_t eva = va + size;
 558
 559         dsb();
 560         va &= ~cpuinfo.dcache_line_mask;
 561         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 562                 _CP15_DCCMVAC(va);
 563         }
 564         dsb();
 565
 566         cpu_l2cache_wb_range(pa, size);
 567 }
 568
 569 /* Write back and invalidate D-cache to PoC */
 570 static __inline void
 571 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 572 {
 573         vm_offset_t va;
 574         vm_offset_t eva = sva + size;
 575
 576         dsb();
 577         /* write back L1 first */
 578         va = sva & ~cpuinfo.dcache_line_mask;
 579         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 580                 _CP15_DCCMVAC(va);
 581         }
 582         dsb();
 583
 584         /* then write back and invalidate L2 */
 585         cpu_l2cache_wbinv_range(pa, size);
 586
 587         /* then invalidate L1 */
 588         va = sva & ~cpuinfo.dcache_line_mask;
 589         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 590                 _CP15_DCIMVAC(va);
 591         }
 592         dsb();
 593 }
 594
 595 /* Set TTB0 register */
 596 static __inline void
 597 cp15_ttbr_set(uint32_t reg)
 598 {
 599         dsb();
 600         _CP15_TTB_SET(reg);
 601         dsb();
 602         _CP15_BPIALL();
 603         dsb();
 604         isb();
 605         tlb_flush_all_ng_local();
 606 }
 607
 608 /*
 609  * Functions for address checking:
 610  *
 611  *  cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access
 612  *  cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access
 613  *  cp15_ats1cur_check() ... check stage 1 unprivileged (PL0) read access
 614  *  cp15_ats1cuw_check() ... check stage 1 unprivileged (PL0) write access
 615  *
 616  * They must be called while interrupts are disabled to get consistent result.
 617  */
 618 static __inline int
 619 cp15_ats1cpr_check(vm_offset_t addr)
 620 {
 621
 622         cp15_ats1cpr_set(addr);
 623         isb();
 624         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 625 }
 626
 627 static __inline int
 628 cp15_ats1cpw_check(vm_offset_t addr)
 629 {
 630
 631         cp15_ats1cpw_set(addr);
 632         isb();
 633         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 634 }
 635
 636 static __inline int
 637 cp15_ats1cur_check(vm_offset_t addr)
 638 {
 639
 640         cp15_ats1cur_set(addr);
 641         isb();
 642         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 643 }
 644
 645 static __inline int
 646 cp15_ats1cuw_check(vm_offset_t addr)
 647 {
 648
 649         cp15_ats1cuw_set(addr);
 650         isb();
 651         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 652 }
 653 #endif /* !__ARM_ARCH < 6 */
 654
 655 #endif /* !MACHINE_CPU_V6_H */