sys/arm/include/cpu-v6.h

   1 /*-
   2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
   3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 #ifndef MACHINE_CPU_V6_H
  30 #define MACHINE_CPU_V6_H
  31
  32 #include "machine/atomic.h"
  33 #include "machine/cpufunc.h"
  34 #include "machine/cpuinfo.h"
  35 #include "machine/sysreg.h"
  36
  37
  38 #define CPU_ASID_KERNEL 0
  39
  40 vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
  41 vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
  42
  43 /*
  44  * Macros to generate CP15 (system control processor) read/write functions.
  45  */
  46 #define _FX(s...) #s
  47
  48 #define _RF0(fname, aname...)                                           \
  49 static __inline register_t                                              \
  50 fname(void)                                                             \
  51 {                                                                       \
  52         register_t reg;                                                 \
  53         __asm __volatile("mrc\t" _FX(aname): "=r" (reg));               \
  54         return(reg);                                                    \
  55 }
  56
  57 #define _R64F0(fname, aname)                                            \
  58 static __inline uint64_t                                                \
  59 fname(void)                                                             \
  60 {                                                                       \
  61         uint64_t reg;                                                   \
  62         __asm __volatile("mrrc\t" _FX(aname): "=r" (reg));              \
  63         return(reg);                                                    \
  64 }
  65
  66 #define _WF0(fname, aname...)                                           \
  67 static __inline void                                                    \
  68 fname(void)                                                             \
  69 {                                                                       \
  70         __asm __volatile("mcr\t" _FX(aname));                           \
  71 }
  72
  73 #define _WF1(fname, aname...)                                           \
  74 static __inline void                                                    \
  75 fname(register_t reg)                                                   \
  76 {                                                                       \
  77         __asm __volatile("mcr\t" _FX(aname):: "r" (reg));               \
  78 }
  79
  80 #define _W64F1(fname, aname...)                                         \
  81 static __inline void                                                    \
  82 fname(uint64_t reg)                                                     \
  83 {                                                                       \
  84         __asm __volatile("mcrr\t" _FX(aname):: "r" (reg));              \
  85 }
  86
  87 /*
  88  * Raw CP15  maintenance operations
  89  * !!! not for external use !!!
  90  */
  91
  92 /* TLB */
  93
  94 _WF0(_CP15_TLBIALL, CP15_TLBIALL)               /* Invalidate entire unified TLB */
  95 #if __ARM_ARCH >= 7 && defined SMP
  96 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)           /* Invalidate entire unified TLB IS */
  97 #endif
  98 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))         /* Invalidate unified TLB by ASID */
  99 #if __ARM_ARCH >= 7 && defined SMP
 100 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))     /* Invalidate unified TLB by ASID IS */
 101 #endif
 102 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))         /* Invalidate unified TLB by MVA, all ASID */
 103 #if __ARM_ARCH >= 7 && defined SMP
 104 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))     /* Invalidate unified TLB by MVA, all ASID IS */
 105 #endif
 106 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))           /* Invalidate unified TLB by MVA */
 107
 108 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
 109
 110 /* Cache and Branch predictor */
 111
 112 _WF0(_CP15_BPIALL, CP15_BPIALL)                 /* Branch predictor invalidate all */
 113 #if __ARM_ARCH >= 7 && defined SMP
 114 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS)             /* Branch predictor invalidate all IS */
 115 #endif
 116 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))             /* Branch predictor invalidate by MVA */
 117 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0))         /* Data cache clean and invalidate by MVA PoC */
 118 _WF1(_CP15_DCCISW, CP15_DCCISW(%0))             /* Data cache clean and invalidate by set/way */
 119 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0))           /* Data cache clean by MVA PoC */
 120 #if __ARM_ARCH >= 7
 121 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0))           /* Data cache clean by MVA PoU */
 122 #endif
 123 _WF1(_CP15_DCCSW, CP15_DCCSW(%0))               /* Data cache clean by set/way */
 124 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))           /* Data cache invalidate by MVA PoC */
 125 _WF1(_CP15_DCISW, CP15_DCISW(%0))               /* Data cache invalidate by set/way */
 126 _WF0(_CP15_ICIALLU, CP15_ICIALLU)               /* Instruction cache invalidate all PoU */
 127 #if __ARM_ARCH >= 7 && defined SMP
 128 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS)           /* Instruction cache invalidate all PoU IS */
 129 #endif
 130 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))           /* Instruction cache invalidate */
 131
 132 /*
 133  * Publicly accessible functions
 134  */
 135
 136 /* Various control registers */
 137
 138 _RF0(cp15_dfsr_get, CP15_DFSR(%0))
 139 _RF0(cp15_ifsr_get, CP15_IFSR(%0))
 140 _WF1(cp15_prrr_set, CP15_PRRR(%0))
 141 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
 142 _RF0(cp15_ttbr_get, CP15_TTBR0(%0))
 143 _RF0(cp15_dfar_get, CP15_DFAR(%0))
 144 #if __ARM_ARCH >= 7
 145 _RF0(cp15_ifar_get, CP15_IFAR(%0))
 146 #endif
 147
 148 /*CPU id registers */
 149 _RF0(cp15_midr_get, CP15_MIDR(%0))
 150 _RF0(cp15_ctr_get, CP15_CTR(%0))
 151 _RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
 152 _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
 153 _RF0(cp15_mpidr_get, CP15_MPIDR(%0))
 154 _RF0(cp15_revidr_get, CP15_REVIDR(%0))
 155 _RF0(cp15_aidr_get, CP15_AIDR(%0))
 156 _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
 157 _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
 158 _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
 159 _RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
 160 _RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
 161 _RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
 162 _RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
 163 _RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
 164 _RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
 165 _RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
 166 _RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
 167 _RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
 168 _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
 169 _RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
 170 _RF0(cp15_cbar_get, CP15_CBAR(%0))
 171
 172 /* Performance Monitor registers */
 173
 174 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
 175 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 176 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 177 #elif __ARM_ARCH > 6
 178 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 179 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 180 _RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
 181 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
 182 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
 183 _RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
 184 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
 185 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
 186 _RF0(cp15_pmselr_get, CP15_PMSELR(%0))
 187 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
 188 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 189 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 190 _RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
 191 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
 192 _RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
 193 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
 194 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 195 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 196 _RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
 197 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
 198 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
 199 #endif
 200
 201 _RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
 202 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
 203 _RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
 204 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
 205 _RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
 206 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
 207
 208 /* Generic Timer registers - only use when you know the hardware is available */
 209 _RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
 210 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
 211 _RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
 212 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
 213 _RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
 214 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
 215 _RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
 216 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
 217 _RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
 218 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
 219 _RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
 220 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
 221 _RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
 222 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
 223 _RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
 224 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
 225 _RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
 226 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
 227
 228 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
 229 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
 230 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
 231 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
 232 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
 233 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
 234 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
 235 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
 236 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
 237 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
 238
 239 #undef  _FX
 240 #undef  _RF0
 241 #undef  _WF0
 242 #undef  _WF1
 243
 244 /*
 245  * TLB maintenance operations.
 246  */
 247
 248 /* Local (i.e. not broadcasting ) operations.  */
 249
 250 /* Flush all TLB entries (even global). */
 251 static __inline void
 252 tlb_flush_all_local(void)
 253 {
 254
 255         dsb();
 256         _CP15_TLBIALL();
 257         dsb();
 258 }
 259
 260 /* Flush all not global TLB entries. */
 261 static __inline void
 262 tlb_flush_all_ng_local(void)
 263 {
 264
 265         dsb();
 266         _CP15_TLBIASID(CPU_ASID_KERNEL);
 267         dsb();
 268 }
 269
 270 /* Flush single TLB entry (even global). */
 271 static __inline void
 272 tlb_flush_local(vm_offset_t sva)
 273 {
 274
 275         dsb();
 276         _CP15_TLBIMVA((sva & ~PAGE_MASK ) | CPU_ASID_KERNEL);
 277         dsb();
 278 }
 279
 280 /* Flush range of TLB entries (even global). */
 281 static __inline void
 282 tlb_flush_range_local(vm_offset_t sva, vm_size_t size)
 283 {
 284         vm_offset_t va;
 285         vm_offset_t eva = sva + size;
 286
 287         dsb();
 288         for (va = sva; va < eva; va += PAGE_SIZE)
 289                 _CP15_TLBIMVA((va & ~PAGE_MASK ) | CPU_ASID_KERNEL);
 290         dsb();
 291 }
 292
 293 /* Broadcasting operations. */
 294 #if __ARM_ARCH >= 7 && defined SMP
 295
 296 static __inline void
 297 tlb_flush_all(void)
 298 {
 299
 300         dsb();
 301         _CP15_TLBIALLIS();
 302         dsb();
 303 }
 304
 305 static __inline void
 306 tlb_flush_all_ng(void)
 307 {
 308
 309         dsb();
 310         _CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 311         dsb();
 312 }
 313
 314 static __inline void
 315 tlb_flush(vm_offset_t sva)
 316 {
 317
 318         dsb();
 319         _CP15_TLBIMVAAIS(sva);
 320         dsb();
 321 }
 322
 323 static __inline void
 324 tlb_flush_range(vm_offset_t sva,  vm_size_t size)
 325 {
 326         vm_offset_t va;
 327         vm_offset_t eva = sva + size;
 328
 329         dsb();
 330         for (va = sva; va < eva; va += PAGE_SIZE)
 331                 _CP15_TLBIMVAAIS(va);
 332         dsb();
 333 }
 334 #else /* SMP */
 335
 336 #define tlb_flush_all()                 tlb_flush_all_local()
 337 #define tlb_flush_all_ng()              tlb_flush_all_ng_local()
 338 #define tlb_flush(sva)                  tlb_flush_local(sva)
 339 #define tlb_flush_range(sva, size)      tlb_flush_range_local(sva, size)
 340
 341 #endif /* SMP */
 342
 343 /*
 344  * Cache maintenance operations.
 345  */
 346
 347 /*  Sync I and D caches to PoU */
 348 static __inline void
 349 icache_sync(vm_offset_t sva, vm_size_t size)
 350 {
 351         vm_offset_t va;
 352         vm_offset_t eva = sva + size;
 353
 354         dsb();
 355         for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
 356 #if __ARM_ARCH >= 7 && defined SMP
 357                 _CP15_DCCMVAU(va);
 358 #else
 359                 _CP15_DCCMVAC(va);
 360 #endif
 361         }
 362         dsb();
 363 #if __ARM_ARCH >= 7 && defined SMP
 364         _CP15_ICIALLUIS();
 365 #else
 366         _CP15_ICIALLU();
 367 #endif
 368         dsb();
 369         isb();
 370 }
 371
 372 /*  Invalidate I cache */
 373 static __inline void
 374 icache_inv_all(void)
 375 {
 376 #if __ARM_ARCH >= 7 && defined SMP
 377         _CP15_ICIALLUIS();
 378 #else
 379         _CP15_ICIALLU();
 380 #endif
 381         dsb();
 382         isb();
 383 }
 384
 385 /* Invalidate branch predictor buffer */
 386 static __inline void
 387 bpb_inv_all(void)
 388 {
 389 #if __ARM_ARCH >= 7 && defined SMP
 390         _CP15_BPIALLIS();
 391 #else
 392         _CP15_BPIALL();
 393 #endif
 394         dsb();
 395         isb();
 396 }
 397
 398 /* Write back D-cache to PoU */
 399 static __inline void
 400 dcache_wb_pou(vm_offset_t sva, vm_size_t size)
 401 {
 402         vm_offset_t va;
 403         vm_offset_t eva = sva + size;
 404
 405         dsb();
 406         for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
 407 #if __ARM_ARCH >= 7 && defined SMP
 408                 _CP15_DCCMVAU(va);
 409 #else
 410                 _CP15_DCCMVAC(va);
 411 #endif
 412         }
 413         dsb();
 414 }
 415
 416 /* Invalidate D-cache to PoC */
 417 static __inline void
 418 dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 419 {
 420         vm_offset_t va;
 421         vm_offset_t eva = sva + size;
 422
 423         /* invalidate L1 first */
 424         for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
 425                 _CP15_DCIMVAC(va);
 426         }
 427         dsb();
 428
 429         /* then L2 */
 430         cpu_l2cache_inv_range(pa, size);
 431         dsb();
 432
 433         /* then L1 again */
 434         for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
 435                 _CP15_DCIMVAC(va);
 436         }
 437         dsb();
 438 }
 439
 440 /* Write back D-cache to PoC */
 441 static __inline void
 442 dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 443 {
 444         vm_offset_t va;
 445         vm_offset_t eva = sva + size;
 446
 447         dsb();
 448
 449         for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
 450                 _CP15_DCCMVAC(va);
 451         }
 452         dsb();
 453
 454         cpu_l2cache_wb_range(pa, size);
 455 }
 456
 457 /* Write back and invalidate D-cache to PoC */
 458 static __inline void
 459 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 460 {
 461         vm_offset_t va;
 462         vm_offset_t eva = sva + size;
 463
 464         dsb();
 465
 466         /* write back L1 first */
 467         for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
 468                 _CP15_DCCMVAC(va);
 469         }
 470         dsb();
 471
 472         /* then write back and invalidate L2 */
 473         cpu_l2cache_wbinv_range(pa, size);
 474
 475         /* then invalidate L1 */
 476         for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
 477                 _CP15_DCIMVAC(va);
 478         }
 479         dsb();
 480 }
 481
 482 /* Set TTB0 register */
 483 static __inline void
 484 cp15_ttbr_set(uint32_t reg)
 485 {
 486         dsb();
 487         _CP15_TTB_SET(reg);
 488         dsb();
 489         _CP15_BPIALL();
 490         dsb();
 491         isb();
 492         tlb_flush_all_ng_local();
 493 }
 494
 495 #endif /* !MACHINE_CPU_V6_H */