sys/arm/include/cpu-v6.h

   1 /*-
   2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
   3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 #ifndef MACHINE_CPU_V6_H
  30 #define MACHINE_CPU_V6_H
  31
  32 /* There are no user serviceable parts here, they may change without notice */
  33 #ifndef _KERNEL
  34 #error Only include this file in the kernel
  35 #endif
  36
  37 #include <machine/atomic.h>
  38 #include <machine/cpufunc.h>
  39 #include <machine/cpuinfo.h>
  40 #include <machine/sysreg.h>
  41
  42 #if __ARM_ARCH < 6
  43 #error Only include this file for ARMv6
  44 #else
  45
  46 #define CPU_ASID_KERNEL 0
  47
  48 #if __ARM_ARCH >= 7
  49 #if !defined(SMP)
  50 /* No SMP so no need to use the MP extensions */
  51 #define ARM_USE_MP_EXTENSIONS   0
  52 #elif defined(CPU_CORTEXA8) && \
  53     (defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B))
  54 #define ARM_USE_MP_EXTENSIONS   (cpuinfo.mp_ext != 0)
  55 #elif defined(CPU_CORTEXA8)
  56 #define ARM_USE_MP_EXTENSIONS   0
  57 #else
  58 #define ARM_USE_MP_EXTENSIONS   1
  59 #endif
  60 #endif /* __ARM_ARCH >= 7 */
  61
  62
  63 void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
  64 vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
  65 vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
  66
  67 #ifdef DEV_PMU
  68 #include <sys/pcpu.h>
  69 #define PMU_OVSR_C              0x80000000      /* Cycle Counter */
  70 extern uint32_t ccnt_hi[MAXCPU];
  71 extern int pmu_attched;
  72 #endif /* DEV_PMU */
  73
  74 #define sev()  __asm __volatile("sev" : : : "memory")
  75 #define wfe()  __asm __volatile("wfe" : : : "memory")
  76
  77 /*
  78  * Macros to generate CP15 (system control processor) read/write functions.
  79  */
  80 #define _FX(s...) #s
  81
  82 #define _RF0(fname, aname...)                                           \
  83 static __inline register_t                                              \
  84 fname(void)                                                             \
  85 {                                                                       \
  86         register_t reg;                                                 \
  87         __asm __volatile("mrc\t" _FX(aname): "=r" (reg));               \
  88         return(reg);                                                    \
  89 }
  90
  91 #define _R64F0(fname, aname)                                            \
  92 static __inline uint64_t                                                \
  93 fname(void)                                                             \
  94 {                                                                       \
  95         uint64_t reg;                                                   \
  96         __asm __volatile("mrrc\t" _FX(aname): "=r" (reg));              \
  97         return(reg);                                                    \
  98 }
  99
 100 #define _WF0(fname, aname...)                                           \
 101 static __inline void                                                    \
 102 fname(void)                                                             \
 103 {                                                                       \
 104         __asm __volatile("mcr\t" _FX(aname));                           \
 105 }
 106
 107 #define _WF1(fname, aname...)                                           \
 108 static __inline void                                                    \
 109 fname(register_t reg)                                                   \
 110 {                                                                       \
 111         __asm __volatile("mcr\t" _FX(aname):: "r" (reg));               \
 112 }
 113
 114 #define _W64F1(fname, aname...)                                         \
 115 static __inline void                                                    \
 116 fname(uint64_t reg)                                                     \
 117 {                                                                       \
 118         __asm __volatile("mcrr\t" _FX(aname):: "r" (reg));              \
 119 }
 120
 121 /*
 122  * Raw CP15  maintenance operations
 123  * !!! not for external use !!!
 124  */
 125
 126 /* TLB */
 127
 128 _WF0(_CP15_TLBIALL, CP15_TLBIALL)               /* Invalidate entire unified TLB */
 129 #if __ARM_ARCH >= 7
 130 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)           /* Invalidate entire unified TLB IS */
 131 #endif
 132 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))         /* Invalidate unified TLB by ASID */
 133 #if __ARM_ARCH >= 7
 134 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))     /* Invalidate unified TLB by ASID IS */
 135 #endif
 136 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))         /* Invalidate unified TLB by MVA, all ASID */
 137 #if __ARM_ARCH >= 7
 138 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))     /* Invalidate unified TLB by MVA, all ASID IS */
 139 #endif
 140 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))           /* Invalidate unified TLB by MVA */
 141
 142 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
 143
 144 /* Cache and Branch predictor */
 145
 146 _WF0(_CP15_BPIALL, CP15_BPIALL)                 /* Branch predictor invalidate all */
 147 #if __ARM_ARCH >= 7
 148 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS)             /* Branch predictor invalidate all IS */
 149 #endif
 150 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))             /* Branch predictor invalidate by MVA */
 151 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0))         /* Data cache clean and invalidate by MVA PoC */
 152 _WF1(_CP15_DCCISW, CP15_DCCISW(%0))             /* Data cache clean and invalidate by set/way */
 153 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0))           /* Data cache clean by MVA PoC */
 154 #if __ARM_ARCH >= 7
 155 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0))           /* Data cache clean by MVA PoU */
 156 #endif
 157 _WF1(_CP15_DCCSW, CP15_DCCSW(%0))               /* Data cache clean by set/way */
 158 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))           /* Data cache invalidate by MVA PoC */
 159 _WF1(_CP15_DCISW, CP15_DCISW(%0))               /* Data cache invalidate by set/way */
 160 _WF0(_CP15_ICIALLU, CP15_ICIALLU)               /* Instruction cache invalidate all PoU */
 161 #if __ARM_ARCH >= 7
 162 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS)           /* Instruction cache invalidate all PoU IS */
 163 #endif
 164 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))           /* Instruction cache invalidate */
 165
 166 /*
 167  * Publicly accessible functions
 168  */
 169
 170 /* CP14 Debug Registers */
 171 _RF0(cp14_dbgdidr_get, CP14_DBGDIDR(%0))
 172 _RF0(cp14_dbgprsr_get, CP14_DBGPRSR(%0))
 173 _RF0(cp14_dbgoslsr_get, CP14_DBGOSLSR(%0))
 174 _RF0(cp14_dbgosdlr_get, CP14_DBGOSDLR(%0))
 175 _RF0(cp14_dbgdscrint_get, CP14_DBGDSCRint(%0))
 176
 177 _WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0))
 178 _WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0))
 179 _WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0))
 180 _WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0))
 181
 182 /* Various control registers */
 183
 184 _RF0(cp15_cpacr_get, CP15_CPACR(%0))
 185 _WF1(cp15_cpacr_set, CP15_CPACR(%0))
 186 _RF0(cp15_dfsr_get, CP15_DFSR(%0))
 187 _RF0(cp15_ifsr_get, CP15_IFSR(%0))
 188 _WF1(cp15_prrr_set, CP15_PRRR(%0))
 189 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
 190 _RF0(cp15_ttbr_get, CP15_TTBR0(%0))
 191 _RF0(cp15_dfar_get, CP15_DFAR(%0))
 192 #if __ARM_ARCH >= 7
 193 _RF0(cp15_ifar_get, CP15_IFAR(%0))
 194 _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
 195 #endif
 196 _RF0(cp15_actlr_get, CP15_ACTLR(%0))
 197 _WF1(cp15_actlr_set, CP15_ACTLR(%0))
 198 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
 199 _WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
 200 _WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0))
 201 _WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0))
 202 _RF0(cp15_par_get, CP15_PAR(%0))
 203 _RF0(cp15_sctlr_get, CP15_SCTLR(%0))
 204
 205 /*CPU id registers */
 206 _RF0(cp15_midr_get, CP15_MIDR(%0))
 207 _RF0(cp15_ctr_get, CP15_CTR(%0))
 208 _RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
 209 _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
 210 _RF0(cp15_mpidr_get, CP15_MPIDR(%0))
 211 _RF0(cp15_revidr_get, CP15_REVIDR(%0))
 212 _RF0(cp15_ccsidr_get, CP15_CCSIDR(%0))
 213 _RF0(cp15_clidr_get, CP15_CLIDR(%0))
 214 _RF0(cp15_aidr_get, CP15_AIDR(%0))
 215 _WF1(cp15_csselr_set, CP15_CSSELR(%0))
 216 _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
 217 _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
 218 _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
 219 _RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
 220 _RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
 221 _RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
 222 _RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
 223 _RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
 224 _RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
 225 _RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
 226 _RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
 227 _RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
 228 _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
 229 _RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
 230 _RF0(cp15_cbar_get, CP15_CBAR(%0))
 231
 232 /* Performance Monitor registers */
 233
 234 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
 235 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 236 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 237 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 238 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 239 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 240 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 241 #elif __ARM_ARCH > 6
 242 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 243 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 244 _RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
 245 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
 246 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
 247 _RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
 248 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
 249 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
 250 _RF0(cp15_pmselr_get, CP15_PMSELR(%0))
 251 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
 252 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 253 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 254 _RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
 255 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
 256 _RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
 257 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
 258 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 259 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 260 _RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
 261 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
 262 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
 263 #endif
 264
 265 _RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
 266 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
 267 _RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
 268 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
 269 _RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
 270 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
 271
 272 /* Generic Timer registers - only use when you know the hardware is available */
 273 _RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
 274 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
 275 _RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
 276 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
 277 _RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
 278 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
 279 _RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
 280 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
 281 _RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
 282 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
 283 _RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
 284 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
 285 _RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
 286 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
 287 _RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
 288 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
 289 _RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
 290 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
 291
 292 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
 293 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
 294 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
 295 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
 296 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
 297 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
 298 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
 299 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
 300 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
 301 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
 302
 303 #undef  _FX
 304 #undef  _RF0
 305 #undef  _WF0
 306 #undef  _WF1
 307
 308 /*
 309  * TLB maintenance operations.
 310  */
 311
 312 /* Local (i.e. not broadcasting ) operations.  */
 313
 314 /* Flush all TLB entries (even global). */
 315 static __inline void
 316 tlb_flush_all_local(void)
 317 {
 318
 319         dsb();
 320         _CP15_TLBIALL();
 321         dsb();
 322 }
 323
 324 /* Flush all not global TLB entries. */
 325 static __inline void
 326 tlb_flush_all_ng_local(void)
 327 {
 328
 329         dsb();
 330         _CP15_TLBIASID(CPU_ASID_KERNEL);
 331         dsb();
 332 }
 333
 334 /* Flush single TLB entry (even global). */
 335 static __inline void
 336 tlb_flush_local(vm_offset_t va)
 337 {
 338
 339         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 340
 341         dsb();
 342         _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 343         dsb();
 344 }
 345
 346 /* Flush range of TLB entries (even global). */
 347 static __inline void
 348 tlb_flush_range_local(vm_offset_t va, vm_size_t size)
 349 {
 350         vm_offset_t eva = va + size;
 351
 352         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 353         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 354             size));
 355
 356         dsb();
 357         for (; va < eva; va += PAGE_SIZE)
 358                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 359         dsb();
 360 }
 361
 362 /* Broadcasting operations. */
 363 #if __ARM_ARCH >= 7
 364
 365 static __inline void
 366 tlb_flush_all(void)
 367 {
 368
 369         dsb();
 370         if (ARM_USE_MP_EXTENSIONS)
 371                 _CP15_TLBIALLIS();
 372         else
 373                 _CP15_TLBIALL();
 374         dsb();
 375 }
 376
 377 static __inline void
 378 tlb_flush_all_ng(void)
 379 {
 380
 381         dsb();
 382         if (ARM_USE_MP_EXTENSIONS)
 383                 _CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 384         else
 385                 _CP15_TLBIASID(CPU_ASID_KERNEL);
 386         dsb();
 387 }
 388
 389 static __inline void
 390 tlb_flush(vm_offset_t va)
 391 {
 392
 393         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 394
 395         dsb();
 396         if (ARM_USE_MP_EXTENSIONS)
 397                 _CP15_TLBIMVAAIS(va);
 398         else
 399                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 400         dsb();
 401 }
 402
 403 static __inline void
 404 tlb_flush_range(vm_offset_t va,  vm_size_t size)
 405 {
 406         vm_offset_t eva = va + size;
 407
 408         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 409         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 410             size));
 411
 412         dsb();
 413         if (ARM_USE_MP_EXTENSIONS) {
 414                 for (; va < eva; va += PAGE_SIZE)
 415                         _CP15_TLBIMVAAIS(va);
 416         } else {
 417                 for (; va < eva; va += PAGE_SIZE)
 418                         _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 419         }
 420         dsb();
 421 }
 422 #else /* __ARM_ARCH < 7 */
 423
 424 #define tlb_flush_all()                 tlb_flush_all_local()
 425 #define tlb_flush_all_ng()              tlb_flush_all_ng_local()
 426 #define tlb_flush(va)                   tlb_flush_local(va)
 427 #define tlb_flush_range(va, size)       tlb_flush_range_local(va, size)
 428
 429 #endif /* __ARM_ARCH < 7 */
 430
 431 /*
 432  * Cache maintenance operations.
 433  */
 434
 435 /*  Sync I and D caches to PoU */
 436 static __inline void
 437 icache_sync(vm_offset_t va, vm_size_t size)
 438 {
 439         vm_offset_t eva = va + size;
 440
 441         dsb();
 442         va &= ~cpuinfo.dcache_line_mask;
 443 #if __ARM_ARCH >= 7
 444         if (ARM_USE_MP_EXTENSIONS) {
 445                 for ( ; va < eva; va += cpuinfo.dcache_line_size)
 446                         _CP15_DCCMVAU(va);
 447         } else
 448 #endif
 449         {
 450                 for ( ; va < eva; va += cpuinfo.dcache_line_size)
 451                         _CP15_DCCMVAC(va);
 452         }
 453         dsb();
 454 #if __ARM_ARCH >= 7
 455         if (ARM_USE_MP_EXTENSIONS)
 456                 _CP15_ICIALLUIS();
 457         else
 458 #endif
 459                 _CP15_ICIALLU();
 460         dsb();
 461         isb();
 462 }
 463
 464 /*  Invalidate I cache */
 465 static __inline void
 466 icache_inv_all(void)
 467 {
 468 #if __ARM_ARCH >= 7
 469         if (ARM_USE_MP_EXTENSIONS)
 470                 _CP15_ICIALLUIS();
 471         else
 472 #endif
 473                 _CP15_ICIALLU();
 474         dsb();
 475         isb();
 476 }
 477
 478 /* Invalidate branch predictor buffer */
 479 static __inline void
 480 bpb_inv_all(void)
 481 {
 482 #if __ARM_ARCH >= 7
 483         if (ARM_USE_MP_EXTENSIONS)
 484                 _CP15_BPIALLIS();
 485         else
 486 #endif
 487                 _CP15_BPIALL();
 488         dsb();
 489         isb();
 490 }
 491
 492 /* Write back D-cache to PoU */
 493 static __inline void
 494 dcache_wb_pou(vm_offset_t va, vm_size_t size)
 495 {
 496         vm_offset_t eva = va + size;
 497
 498         dsb();
 499         va &= ~cpuinfo.dcache_line_mask;
 500 #if __ARM_ARCH >= 7
 501         if (ARM_USE_MP_EXTENSIONS) {
 502                 for ( ; va < eva; va += cpuinfo.dcache_line_size)
 503                         _CP15_DCCMVAU(va);
 504         } else
 505 #endif
 506         {
 507                 for ( ; va < eva; va += cpuinfo.dcache_line_size)
 508                         _CP15_DCCMVAC(va);
 509         }
 510         dsb();
 511 }
 512
 513 /*
 514  * Invalidate D-cache to PoC
 515  *
 516  * Caches are invalidated from outermost to innermost as fresh cachelines
 517  * flow in this direction. In given range, if there was no dirty cacheline
 518  * in any cache before, no stale cacheline should remain in them after this
 519  * operation finishes.
 520  */
 521 static __inline void
 522 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 523 {
 524         vm_offset_t eva = va + size;
 525
 526         dsb();
 527         /* invalidate L2 first */
 528         cpu_l2cache_inv_range(pa, size);
 529
 530         /* then L1 */
 531         va &= ~cpuinfo.dcache_line_mask;
 532         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 533                 _CP15_DCIMVAC(va);
 534         }
 535         dsb();
 536 }
 537
 538 /*
 539  * Discard D-cache lines to PoC, prior to overwrite by DMA engine.
 540  *
 541  * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't
 542  * flow into L1 while invalidating.  This routine is intended to be used only
 543  * when invalidating a buffer before a DMA operation loads new data into memory.
 544  * The concern in this case is that dirty lines are not evicted to main memory,
 545  * overwriting the DMA data.  For that reason, the L1 is done first to ensure
 546  * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned.
 547  */
 548 static __inline void
 549 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 550 {
 551         vm_offset_t eva = va + size;
 552
 553         /* invalidate L1 first */
 554         dsb();
 555         va &= ~cpuinfo.dcache_line_mask;
 556         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 557                 _CP15_DCIMVAC(va);
 558         }
 559         dsb();
 560
 561         /* then L2 */
 562         cpu_l2cache_inv_range(pa, size);
 563 }
 564
 565 /*
 566  * Write back D-cache to PoC
 567  *
 568  * Caches are written back from innermost to outermost as dirty cachelines
 569  * flow in this direction. In given range, no dirty cacheline should remain
 570  * in any cache after this operation finishes.
 571  */
 572 static __inline void
 573 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 574 {
 575         vm_offset_t eva = va + size;
 576
 577         dsb();
 578         va &= ~cpuinfo.dcache_line_mask;
 579         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 580                 _CP15_DCCMVAC(va);
 581         }
 582         dsb();
 583
 584         cpu_l2cache_wb_range(pa, size);
 585 }
 586
 587 /* Write back and invalidate D-cache to PoC */
 588 static __inline void
 589 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 590 {
 591         vm_offset_t va;
 592         vm_offset_t eva = sva + size;
 593
 594         dsb();
 595         /* write back L1 first */
 596         va = sva & ~cpuinfo.dcache_line_mask;
 597         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 598                 _CP15_DCCMVAC(va);
 599         }
 600         dsb();
 601
 602         /* then write back and invalidate L2 */
 603         cpu_l2cache_wbinv_range(pa, size);
 604
 605         /* then invalidate L1 */
 606         va = sva & ~cpuinfo.dcache_line_mask;
 607         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 608                 _CP15_DCIMVAC(va);
 609         }
 610         dsb();
 611 }
 612
 613 /* Set TTB0 register */
 614 static __inline void
 615 cp15_ttbr_set(uint32_t reg)
 616 {
 617         dsb();
 618         _CP15_TTB_SET(reg);
 619         dsb();
 620         _CP15_BPIALL();
 621         dsb();
 622         isb();
 623         tlb_flush_all_ng_local();
 624 }
 625
 626 /*
 627  * Functions for address checking:
 628  *
 629  *  cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access
 630  *  cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access
 631  *  cp15_ats1cur_check() ... check stage 1 unprivileged (PL0) read access
 632  *  cp15_ats1cuw_check() ... check stage 1 unprivileged (PL0) write access
 633  *
 634  * They must be called while interrupts are disabled to get consistent result.
 635  */
 636 static __inline int
 637 cp15_ats1cpr_check(vm_offset_t addr)
 638 {
 639
 640         cp15_ats1cpr_set(addr);
 641         isb();
 642         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 643 }
 644
 645 static __inline int
 646 cp15_ats1cpw_check(vm_offset_t addr)
 647 {
 648
 649         cp15_ats1cpw_set(addr);
 650         isb();
 651         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 652 }
 653
 654 static __inline int
 655 cp15_ats1cur_check(vm_offset_t addr)
 656 {
 657
 658         cp15_ats1cur_set(addr);
 659         isb();
 660         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 661 }
 662
 663 static __inline int
 664 cp15_ats1cuw_check(vm_offset_t addr)
 665 {
 666
 667         cp15_ats1cuw_set(addr);
 668         isb();
 669         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 670 }
 671 #endif /* !__ARM_ARCH < 6 */
 672
 673 #endif /* !MACHINE_CPU_V6_H */