2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef MACHINE_CPU_V6_H
30 #define MACHINE_CPU_V6_H
32 /* There are no user serviceable parts here, they may change without notice */
34 #error Only include this file in the kernel
37 #include "machine/atomic.h"
38 #include "machine/cpufunc.h"
39 #include "machine/cpuinfo.h"
40 #include "machine/sysreg.h"
42 #define CPU_ASID_KERNEL 0
44 vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
45 vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
48 * Macros to generate CP15 (system control processor) read/write functions.
52 #define _RF0(fname, aname...) \
53 static __inline register_t \
57 __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \
61 #define _R64F0(fname, aname) \
62 static __inline uint64_t \
66 __asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
70 #define _WF0(fname, aname...) \
71 static __inline void \
74 __asm __volatile("mcr\t" _FX(aname)); \
77 #define _WF1(fname, aname...) \
78 static __inline void \
79 fname(register_t reg) \
81 __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
84 #define _W64F1(fname, aname...) \
85 static __inline void \
88 __asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \
92 * Raw CP15 maintenance operations
93 * !!! not for external use !!!
98 _WF0(_CP15_TLBIALL, CP15_TLBIALL) /* Invalidate entire unified TLB */
99 #if __ARM_ARCH >= 7 && defined SMP
100 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) /* Invalidate entire unified TLB IS */
102 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) /* Invalidate unified TLB by ASID */
103 #if __ARM_ARCH >= 7 && defined SMP
104 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) /* Invalidate unified TLB by ASID IS */
106 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) /* Invalidate unified TLB by MVA, all ASID */
107 #if __ARM_ARCH >= 7 && defined SMP
108 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) /* Invalidate unified TLB by MVA, all ASID IS */
110 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) /* Invalidate unified TLB by MVA */
112 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
114 /* Cache and Branch predictor */
116 _WF0(_CP15_BPIALL, CP15_BPIALL) /* Branch predictor invalidate all */
117 #if __ARM_ARCH >= 7 && defined SMP
118 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS) /* Branch predictor invalidate all IS */
120 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0)) /* Branch predictor invalidate by MVA */
121 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0)) /* Data cache clean and invalidate by MVA PoC */
122 _WF1(_CP15_DCCISW, CP15_DCCISW(%0)) /* Data cache clean and invalidate by set/way */
123 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0)) /* Data cache clean by MVA PoC */
125 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0)) /* Data cache clean by MVA PoU */
127 _WF1(_CP15_DCCSW, CP15_DCCSW(%0)) /* Data cache clean by set/way */
128 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0)) /* Data cache invalidate by MVA PoC */
129 _WF1(_CP15_DCISW, CP15_DCISW(%0)) /* Data cache invalidate by set/way */
130 _WF0(_CP15_ICIALLU, CP15_ICIALLU) /* Instruction cache invalidate all PoU */
131 #if __ARM_ARCH >= 7 && defined SMP
132 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS) /* Instruction cache invalidate all PoU IS */
134 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) /* Instruction cache invalidate */
137 * Publicly accessible functions
140 /* Various control registers */
142 _RF0(cp15_cpacr_get, CP15_CPACR(%0))
143 _WF1(cp15_cpacr_set, CP15_CPACR(%0))
144 _RF0(cp15_dfsr_get, CP15_DFSR(%0))
145 _RF0(cp15_ifsr_get, CP15_IFSR(%0))
146 _WF1(cp15_prrr_set, CP15_PRRR(%0))
147 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
148 _RF0(cp15_ttbr_get, CP15_TTBR0(%0))
149 _RF0(cp15_dfar_get, CP15_DFAR(%0))
151 _RF0(cp15_ifar_get, CP15_IFAR(%0))
152 _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
154 /* ARMv6+ and XScale */
155 _RF0(cp15_actlr_get, CP15_ACTLR(%0))
156 _WF1(cp15_actlr_set, CP15_ACTLR(%0))
158 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0));
159 _RF0(cp15_par_get, CP15_PAR);
160 _RF0(cp15_sctlr_get, CP15_SCTLR(%0))
163 /*CPU id registers */
164 _RF0(cp15_midr_get, CP15_MIDR(%0))
165 _RF0(cp15_ctr_get, CP15_CTR(%0))
166 _RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
167 _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
168 _RF0(cp15_mpidr_get, CP15_MPIDR(%0))
169 _RF0(cp15_revidr_get, CP15_REVIDR(%0))
170 _RF0(cp15_ccsidr_get, CP15_CCSIDR(%0))
171 _RF0(cp15_clidr_get, CP15_CLIDR(%0))
172 _RF0(cp15_aidr_get, CP15_AIDR(%0))
173 _WF1(cp15_csselr_set, CP15_CSSELR(%0))
174 _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
175 _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
176 _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
177 _RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
178 _RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
179 _RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
180 _RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
181 _RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
182 _RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
183 _RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
184 _RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
185 _RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
186 _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
187 _RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
188 _RF0(cp15_cbar_get, CP15_CBAR(%0))
190 /* Performance Monitor registers */
192 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
193 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
194 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
195 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
196 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
197 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
198 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
200 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
201 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
202 _RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
203 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
204 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
205 _RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
206 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
207 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
208 _RF0(cp15_pmselr_get, CP15_PMSELR(%0))
209 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
210 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
211 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
212 _RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
213 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
214 _RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
215 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
216 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
217 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
218 _RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
219 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
220 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
223 _RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
224 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
225 _RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
226 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
227 _RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
228 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
230 /* Generic Timer registers - only use when you know the hardware is available */
231 _RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
232 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
233 _RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
234 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
235 _RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
236 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
237 _RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
238 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
239 _RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
240 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
241 _RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
242 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
243 _RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
244 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
245 _RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
246 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
247 _RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
248 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
250 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
251 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
252 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
253 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
254 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
255 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
256 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
257 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
258 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
259 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
267 * TLB maintenance operations.
270 /* Local (i.e. not broadcasting ) operations. */
272 /* Flush all TLB entries (even global). */
274 tlb_flush_all_local(void)
282 /* Flush all not global TLB entries. */
284 tlb_flush_all_ng_local(void)
288 _CP15_TLBIASID(CPU_ASID_KERNEL);
292 /* Flush single TLB entry (even global). */
294 tlb_flush_local(vm_offset_t va)
297 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
300 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
304 /* Flush range of TLB entries (even global). */
306 tlb_flush_range_local(vm_offset_t va, vm_size_t size)
308 vm_offset_t eva = va + size;
310 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
311 KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
315 for (; va < eva; va += PAGE_SIZE)
316 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
320 /* Broadcasting operations. */
321 #if __ARM_ARCH >= 7 && defined SMP
333 tlb_flush_all_ng(void)
337 _CP15_TLBIASIDIS(CPU_ASID_KERNEL);
342 tlb_flush(vm_offset_t va)
345 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
348 _CP15_TLBIMVAAIS(va);
353 tlb_flush_range(vm_offset_t va, vm_size_t size)
355 vm_offset_t eva = va + size;
357 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
358 KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
362 for (; va < eva; va += PAGE_SIZE)
363 _CP15_TLBIMVAAIS(va);
368 #define tlb_flush_all() tlb_flush_all_local()
369 #define tlb_flush_all_ng() tlb_flush_all_ng_local()
370 #define tlb_flush(va) tlb_flush_local(va)
371 #define tlb_flush_range(va, size) tlb_flush_range_local(va, size)
376 * Cache maintenance operations.
379 /* Sync I and D caches to PoU */
381 icache_sync(vm_offset_t va, vm_size_t size)
383 vm_offset_t eva = va + size;
386 va &= ~cpuinfo.dcache_line_mask;
387 for ( ; va < eva; va += cpuinfo.dcache_line_size) {
388 #if __ARM_ARCH >= 7 && defined SMP
395 #if __ARM_ARCH >= 7 && defined SMP
404 /* Invalidate I cache */
408 #if __ARM_ARCH >= 7 && defined SMP
417 /* Invalidate branch predictor buffer */
421 #if __ARM_ARCH >= 7 && defined SMP
430 /* Write back D-cache to PoU */
432 dcache_wb_pou(vm_offset_t va, vm_size_t size)
434 vm_offset_t eva = va + size;
437 va &= ~cpuinfo.dcache_line_mask;
438 for ( ; va < eva; va += cpuinfo.dcache_line_size) {
439 #if __ARM_ARCH >= 7 && defined SMP
449 * Invalidate D-cache to PoC
451 * Caches are invalidated from outermost to innermost as fresh cachelines
452 * flow in this direction. In given range, if there was no dirty cacheline
453 * in any cache before, no stale cacheline should remain in them after this
454 * operation finishes.
457 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
459 vm_offset_t eva = va + size;
462 /* invalidate L2 first */
463 cpu_l2cache_inv_range(pa, size);
466 va &= ~cpuinfo.dcache_line_mask;
467 for ( ; va < eva; va += cpuinfo.dcache_line_size) {
474 * Discard D-cache lines to PoC, prior to overwrite by DMA engine
476 * Invalidate caches, discarding data in dirty lines. This is useful
477 * if the memory is about to be overwritten, e.g. by a DMA engine.
478 * Invalidate caches from innermost to outermost to follow the flow
479 * of dirty cachelines.
482 dcache_dma_preread(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
484 vm_offset_t eva = va + size;
486 /* invalidate L1 first */
488 va &= ~cpuinfo.dcache_line_mask;
489 for ( ; va < eva; va += cpuinfo.dcache_line_size) {
495 cpu_l2cache_inv_range(pa, size);
499 * Write back D-cache to PoC
501 * Caches are written back from innermost to outermost as dirty cachelines
502 * flow in this direction. In given range, no dirty cacheline should remain
503 * in any cache after this operation finishes.
506 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
508 vm_offset_t eva = va + size;
511 va &= ~cpuinfo.dcache_line_mask;
512 for ( ; va < eva; va += cpuinfo.dcache_line_size) {
517 cpu_l2cache_wb_range(pa, size);
520 /* Write back and invalidate D-cache to PoC */
522 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
525 vm_offset_t eva = sva + size;
528 /* write back L1 first */
529 va = sva & ~cpuinfo.dcache_line_mask;
530 for ( ; va < eva; va += cpuinfo.dcache_line_size) {
535 /* then write back and invalidate L2 */
536 cpu_l2cache_wbinv_range(pa, size);
538 /* then invalidate L1 */
539 va = sva & ~cpuinfo.dcache_line_mask;
540 for ( ; va < eva; va += cpuinfo.dcache_line_size) {
546 /* Set TTB0 register */
548 cp15_ttbr_set(uint32_t reg)
556 tlb_flush_all_ng_local();
561 #endif /* !MACHINE_CPU_V6_H */