sys/arm/include/cpu-v6.h

   1 /*-
   2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
   3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 #ifndef MACHINE_CPU_V6_H
  30 #define MACHINE_CPU_V6_H
  31
  32 /* There are no user serviceable parts here, they may change without notice */
  33 #ifndef _KERNEL
  34 #error Only include this file in the kernel
  35 #endif
  36
  37 #include <machine/acle-compat.h>
  38 #include <machine/atomic.h>
  39 #include <machine/cpufunc.h>
  40 #include <machine/cpuinfo.h>
  41 #include <machine/sysreg.h>
  42
  43 #if __ARM_ARCH < 6
  44 #error Only include this file for ARMv6
  45 #else
  46
  47 #define CPU_ASID_KERNEL 0
  48
  49 void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
  50 vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
  51 vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
  52
  53 #ifdef DEV_PMU
  54 #include <sys/pcpu.h>
  55 #define PMU_OVSR_C              0x80000000      /* Cycle Counter */
  56 extern uint32_t ccnt_hi[MAXCPU];
  57 extern int pmu_attched;
  58 #endif /* DEV_PMU */
  59
  60
  61 /*
  62  * Macros to generate CP15 (system control processor) read/write functions.
  63  */
  64 #define _FX(s...) #s
  65
  66 #define _RF0(fname, aname...)                                           \
  67 static __inline register_t                                              \
  68 fname(void)                                                             \
  69 {                                                                       \
  70         register_t reg;                                                 \
  71         __asm __volatile("mrc\t" _FX(aname): "=r" (reg));               \
  72         return(reg);                                                    \
  73 }
  74
  75 #define _R64F0(fname, aname)                                            \
  76 static __inline uint64_t                                                \
  77 fname(void)                                                             \
  78 {                                                                       \
  79         uint64_t reg;                                                   \
  80         __asm __volatile("mrrc\t" _FX(aname): "=r" (reg));              \
  81         return(reg);                                                    \
  82 }
  83
  84 #define _WF0(fname, aname...)                                           \
  85 static __inline void                                                    \
  86 fname(void)                                                             \
  87 {                                                                       \
  88         __asm __volatile("mcr\t" _FX(aname));                           \
  89 }
  90
  91 #define _WF1(fname, aname...)                                           \
  92 static __inline void                                                    \
  93 fname(register_t reg)                                                   \
  94 {                                                                       \
  95         __asm __volatile("mcr\t" _FX(aname):: "r" (reg));               \
  96 }
  97
  98 #define _W64F1(fname, aname...)                                         \
  99 static __inline void                                                    \
 100 fname(uint64_t reg)                                                     \
 101 {                                                                       \
 102         __asm __volatile("mcrr\t" _FX(aname):: "r" (reg));              \
 103 }
 104
 105 /*
 106  * Raw CP15  maintenance operations
 107  * !!! not for external use !!!
 108  */
 109
 110 /* TLB */
 111
 112 _WF0(_CP15_TLBIALL, CP15_TLBIALL)               /* Invalidate entire unified TLB */
 113 #if __ARM_ARCH >= 7 && defined SMP
 114 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)           /* Invalidate entire unified TLB IS */
 115 #endif
 116 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))         /* Invalidate unified TLB by ASID */
 117 #if __ARM_ARCH >= 7 && defined SMP
 118 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))     /* Invalidate unified TLB by ASID IS */
 119 #endif
 120 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))         /* Invalidate unified TLB by MVA, all ASID */
 121 #if __ARM_ARCH >= 7 && defined SMP
 122 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))     /* Invalidate unified TLB by MVA, all ASID IS */
 123 #endif
 124 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))           /* Invalidate unified TLB by MVA */
 125
 126 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
 127
 128 /* Cache and Branch predictor */
 129
 130 _WF0(_CP15_BPIALL, CP15_BPIALL)                 /* Branch predictor invalidate all */
 131 #if __ARM_ARCH >= 7 && defined SMP
 132 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS)             /* Branch predictor invalidate all IS */
 133 #endif
 134 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))             /* Branch predictor invalidate by MVA */
 135 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0))         /* Data cache clean and invalidate by MVA PoC */
 136 _WF1(_CP15_DCCISW, CP15_DCCISW(%0))             /* Data cache clean and invalidate by set/way */
 137 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0))           /* Data cache clean by MVA PoC */
 138 #if __ARM_ARCH >= 7
 139 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0))           /* Data cache clean by MVA PoU */
 140 #endif
 141 _WF1(_CP15_DCCSW, CP15_DCCSW(%0))               /* Data cache clean by set/way */
 142 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))           /* Data cache invalidate by MVA PoC */
 143 _WF1(_CP15_DCISW, CP15_DCISW(%0))               /* Data cache invalidate by set/way */
 144 _WF0(_CP15_ICIALLU, CP15_ICIALLU)               /* Instruction cache invalidate all PoU */
 145 #if __ARM_ARCH >= 7 && defined SMP
 146 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS)           /* Instruction cache invalidate all PoU IS */
 147 #endif
 148 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))           /* Instruction cache invalidate */
 149
 150 /*
 151  * Publicly accessible functions
 152  */
 153
 154 /* CP14 Debug Registers */
 155 _RF0(cp14_dbgdidr_get, CP14_DBGDIDR(%0))
 156 _RF0(cp14_dbgprsr_get, CP14_DBGPRSR(%0))
 157 _RF0(cp14_dbgoslsr_get, CP14_DBGOSLSR(%0))
 158 _RF0(cp14_dbgosdlr_get, CP14_DBGOSDLR(%0))
 159 _RF0(cp14_dbgdscrint_get, CP14_DBGDSCRint(%0))
 160
 161 _WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0))
 162 _WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0))
 163 _WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0))
 164 _WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0))
 165
 166 /* Various control registers */
 167
 168 _RF0(cp15_cpacr_get, CP15_CPACR(%0))
 169 _WF1(cp15_cpacr_set, CP15_CPACR(%0))
 170 _RF0(cp15_dfsr_get, CP15_DFSR(%0))
 171 _RF0(cp15_ifsr_get, CP15_IFSR(%0))
 172 _WF1(cp15_prrr_set, CP15_PRRR(%0))
 173 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
 174 _RF0(cp15_ttbr_get, CP15_TTBR0(%0))
 175 _RF0(cp15_dfar_get, CP15_DFAR(%0))
 176 #if __ARM_ARCH >= 7
 177 _RF0(cp15_ifar_get, CP15_IFAR(%0))
 178 _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
 179 #endif
 180 _RF0(cp15_actlr_get, CP15_ACTLR(%0))
 181 _WF1(cp15_actlr_set, CP15_ACTLR(%0))
 182 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
 183 _WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
 184 _WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0))
 185 _WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0))
 186 _RF0(cp15_par_get, CP15_PAR(%0))
 187 _RF0(cp15_sctlr_get, CP15_SCTLR(%0))
 188
 189 /*CPU id registers */
 190 _RF0(cp15_midr_get, CP15_MIDR(%0))
 191 _RF0(cp15_ctr_get, CP15_CTR(%0))
 192 _RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
 193 _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
 194 _RF0(cp15_mpidr_get, CP15_MPIDR(%0))
 195 _RF0(cp15_revidr_get, CP15_REVIDR(%0))
 196 _RF0(cp15_ccsidr_get, CP15_CCSIDR(%0))
 197 _RF0(cp15_clidr_get, CP15_CLIDR(%0))
 198 _RF0(cp15_aidr_get, CP15_AIDR(%0))
 199 _WF1(cp15_csselr_set, CP15_CSSELR(%0))
 200 _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
 201 _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
 202 _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
 203 _RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
 204 _RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
 205 _RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
 206 _RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
 207 _RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
 208 _RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
 209 _RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
 210 _RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
 211 _RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
 212 _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
 213 _RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
 214 _RF0(cp15_cbar_get, CP15_CBAR(%0))
 215
 216 /* Performance Monitor registers */
 217
 218 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
 219 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 220 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 221 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 222 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 223 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 224 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 225 #elif __ARM_ARCH > 6
 226 _RF0(cp15_pmcr_get, CP15_PMCR(%0))
 227 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
 228 _RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
 229 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
 230 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
 231 _RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
 232 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
 233 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
 234 _RF0(cp15_pmselr_get, CP15_PMSELR(%0))
 235 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
 236 _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
 237 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
 238 _RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
 239 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
 240 _RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
 241 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
 242 _RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
 243 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
 244 _RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
 245 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
 246 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
 247 #endif
 248
 249 _RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
 250 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
 251 _RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
 252 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
 253 _RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
 254 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
 255
 256 /* Generic Timer registers - only use when you know the hardware is available */
 257 _RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
 258 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
 259 _RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
 260 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
 261 _RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
 262 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
 263 _RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
 264 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
 265 _RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
 266 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
 267 _RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
 268 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
 269 _RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
 270 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
 271 _RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
 272 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
 273 _RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
 274 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
 275
 276 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
 277 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
 278 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
 279 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
 280 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
 281 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
 282 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
 283 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
 284 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
 285 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
 286
 287 #undef  _FX
 288 #undef  _RF0
 289 #undef  _WF0
 290 #undef  _WF1
 291
 292 /*
 293  * TLB maintenance operations.
 294  */
 295
 296 /* Local (i.e. not broadcasting ) operations.  */
 297
 298 /* Flush all TLB entries (even global). */
 299 static __inline void
 300 tlb_flush_all_local(void)
 301 {
 302
 303         dsb();
 304         _CP15_TLBIALL();
 305         dsb();
 306 }
 307
 308 /* Flush all not global TLB entries. */
 309 static __inline void
 310 tlb_flush_all_ng_local(void)
 311 {
 312
 313         dsb();
 314         _CP15_TLBIASID(CPU_ASID_KERNEL);
 315         dsb();
 316 }
 317
 318 /* Flush single TLB entry (even global). */
 319 static __inline void
 320 tlb_flush_local(vm_offset_t va)
 321 {
 322
 323         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 324
 325         dsb();
 326         _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 327         dsb();
 328 }
 329
 330 /* Flush range of TLB entries (even global). */
 331 static __inline void
 332 tlb_flush_range_local(vm_offset_t va, vm_size_t size)
 333 {
 334         vm_offset_t eva = va + size;
 335
 336         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 337         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 338             size));
 339
 340         dsb();
 341         for (; va < eva; va += PAGE_SIZE)
 342                 _CP15_TLBIMVA(va | CPU_ASID_KERNEL);
 343         dsb();
 344 }
 345
 346 /* Broadcasting operations. */
 347 #if __ARM_ARCH >= 7 && defined SMP
 348
 349 static __inline void
 350 tlb_flush_all(void)
 351 {
 352
 353         dsb();
 354         _CP15_TLBIALLIS();
 355         dsb();
 356 }
 357
 358 static __inline void
 359 tlb_flush_all_ng(void)
 360 {
 361
 362         dsb();
 363         _CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 364         dsb();
 365 }
 366
 367 static __inline void
 368 tlb_flush(vm_offset_t va)
 369 {
 370
 371         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 372
 373         dsb();
 374         _CP15_TLBIMVAAIS(va);
 375         dsb();
 376 }
 377
 378 static __inline void
 379 tlb_flush_range(vm_offset_t va,  vm_size_t size)
 380 {
 381         vm_offset_t eva = va + size;
 382
 383         KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 384         KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
 385             size));
 386
 387         dsb();
 388         for (; va < eva; va += PAGE_SIZE)
 389                 _CP15_TLBIMVAAIS(va);
 390         dsb();
 391 }
 392 #else /* SMP */
 393
 394 #define tlb_flush_all()                 tlb_flush_all_local()
 395 #define tlb_flush_all_ng()              tlb_flush_all_ng_local()
 396 #define tlb_flush(va)                   tlb_flush_local(va)
 397 #define tlb_flush_range(va, size)       tlb_flush_range_local(va, size)
 398
 399 #endif /* SMP */
 400
 401 /*
 402  * Cache maintenance operations.
 403  */
 404
 405 /*  Sync I and D caches to PoU */
 406 static __inline void
 407 icache_sync(vm_offset_t va, vm_size_t size)
 408 {
 409         vm_offset_t eva = va + size;
 410
 411         dsb();
 412         va &= ~cpuinfo.dcache_line_mask;
 413         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 414 #if __ARM_ARCH >= 7 && defined SMP
 415                 _CP15_DCCMVAU(va);
 416 #else
 417                 _CP15_DCCMVAC(va);
 418 #endif
 419         }
 420         dsb();
 421 #if __ARM_ARCH >= 7 && defined SMP
 422         _CP15_ICIALLUIS();
 423 #else
 424         _CP15_ICIALLU();
 425 #endif
 426         dsb();
 427         isb();
 428 }
 429
 430 /*  Invalidate I cache */
 431 static __inline void
 432 icache_inv_all(void)
 433 {
 434 #if __ARM_ARCH >= 7 && defined SMP
 435         _CP15_ICIALLUIS();
 436 #else
 437         _CP15_ICIALLU();
 438 #endif
 439         dsb();
 440         isb();
 441 }
 442
 443 /* Invalidate branch predictor buffer */
 444 static __inline void
 445 bpb_inv_all(void)
 446 {
 447 #if __ARM_ARCH >= 7 && defined SMP
 448         _CP15_BPIALLIS();
 449 #else
 450         _CP15_BPIALL();
 451 #endif
 452         dsb();
 453         isb();
 454 }
 455
 456 /* Write back D-cache to PoU */
 457 static __inline void
 458 dcache_wb_pou(vm_offset_t va, vm_size_t size)
 459 {
 460         vm_offset_t eva = va + size;
 461
 462         dsb();
 463         va &= ~cpuinfo.dcache_line_mask;
 464         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 465 #if __ARM_ARCH >= 7 && defined SMP
 466                 _CP15_DCCMVAU(va);
 467 #else
 468                 _CP15_DCCMVAC(va);
 469 #endif
 470         }
 471         dsb();
 472 }
 473
 474 /*
 475  * Invalidate D-cache to PoC
 476  *
 477  * Caches are invalidated from outermost to innermost as fresh cachelines
 478  * flow in this direction. In given range, if there was no dirty cacheline
 479  * in any cache before, no stale cacheline should remain in them after this
 480  * operation finishes.
 481  */
 482 static __inline void
 483 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 484 {
 485         vm_offset_t eva = va + size;
 486
 487         dsb();
 488         /* invalidate L2 first */
 489         cpu_l2cache_inv_range(pa, size);
 490
 491         /* then L1 */
 492         va &= ~cpuinfo.dcache_line_mask;
 493         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 494                 _CP15_DCIMVAC(va);
 495         }
 496         dsb();
 497 }
 498
 499 /*
 500  * Discard D-cache lines to PoC, prior to overwrite by DMA engine.
 501  *
 502  * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't
 503  * flow into L1 while invalidating.  This routine is intended to be used only
 504  * when invalidating a buffer before a DMA operation loads new data into memory.
 505  * The concern in this case is that dirty lines are not evicted to main memory,
 506  * overwriting the DMA data.  For that reason, the L1 is done first to ensure
 507  * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned.
 508  */
 509 static __inline void
 510 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 511 {
 512         vm_offset_t eva = va + size;
 513
 514         /* invalidate L1 first */
 515         dsb();
 516         va &= ~cpuinfo.dcache_line_mask;
 517         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 518                 _CP15_DCIMVAC(va);
 519         }
 520         dsb();
 521
 522         /* then L2 */
 523         cpu_l2cache_inv_range(pa, size);
 524 }
 525
 526 /*
 527  * Write back D-cache to PoC
 528  *
 529  * Caches are written back from innermost to outermost as dirty cachelines
 530  * flow in this direction. In given range, no dirty cacheline should remain
 531  * in any cache after this operation finishes.
 532  */
 533 static __inline void
 534 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
 535 {
 536         vm_offset_t eva = va + size;
 537
 538         dsb();
 539         va &= ~cpuinfo.dcache_line_mask;
 540         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 541                 _CP15_DCCMVAC(va);
 542         }
 543         dsb();
 544
 545         cpu_l2cache_wb_range(pa, size);
 546 }
 547
 548 /* Write back and invalidate D-cache to PoC */
 549 static __inline void
 550 dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
 551 {
 552         vm_offset_t va;
 553         vm_offset_t eva = sva + size;
 554
 555         dsb();
 556         /* write back L1 first */
 557         va = sva & ~cpuinfo.dcache_line_mask;
 558         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 559                 _CP15_DCCMVAC(va);
 560         }
 561         dsb();
 562
 563         /* then write back and invalidate L2 */
 564         cpu_l2cache_wbinv_range(pa, size);
 565
 566         /* then invalidate L1 */
 567         va = sva & ~cpuinfo.dcache_line_mask;
 568         for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 569                 _CP15_DCIMVAC(va);
 570         }
 571         dsb();
 572 }
 573
 574 /* Set TTB0 register */
 575 static __inline void
 576 cp15_ttbr_set(uint32_t reg)
 577 {
 578         dsb();
 579         _CP15_TTB_SET(reg);
 580         dsb();
 581         _CP15_BPIALL();
 582         dsb();
 583         isb();
 584         tlb_flush_all_ng_local();
 585 }
 586
 587 /*
 588  * Functions for address checking:
 589  *
 590  *  cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access
 591  *  cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access
 592  *  cp15_ats1cur_check() ... check stage 1 unprivileged (PL0) read access
 593  *  cp15_ats1cuw_check() ... check stage 1 unprivileged (PL0) write access
 594  *
 595  * They must be called while interrupts are disabled to get consistent result.
 596  */
 597 static __inline int
 598 cp15_ats1cpr_check(vm_offset_t addr)
 599 {
 600
 601         cp15_ats1cpr_set(addr);
 602         isb();
 603         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 604 }
 605
 606 static __inline int
 607 cp15_ats1cpw_check(vm_offset_t addr)
 608 {
 609
 610         cp15_ats1cpw_set(addr);
 611         isb();
 612         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 613 }
 614
 615 static __inline int
 616 cp15_ats1cur_check(vm_offset_t addr)
 617 {
 618
 619         cp15_ats1cur_set(addr);
 620         isb();
 621         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 622 }
 623
 624 static __inline int
 625 cp15_ats1cuw_check(vm_offset_t addr)
 626 {
 627
 628         cp15_ats1cuw_set(addr);
 629         isb();
 630         return (cp15_par_get() & 0x01 ? EFAULT : 0);
 631 }
 632 #endif /* !__ARM_ARCH < 6 */
 633
 634 #endif /* !MACHINE_CPU_V6_H */