1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
4 * Copyright (c) 1997 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Prototypes for cpu, mmu and tlb related functions.
44 #ifndef _MACHINE_CPUFUNC_H_
45 #define _MACHINE_CPUFUNC_H_
49 #include <sys/types.h>
50 #include <machine/armreg.h>
51 #include <machine/cpuconf.h>
56 __asm(".word 0xe7ffffff");
59 struct cpu_functions {
63 void (*cf_cpwait) (void);
67 u_int (*cf_control) (u_int bic, u_int eor);
68 void (*cf_setttb) (u_int ttb);
72 void (*cf_tlb_flushID) (void);
73 void (*cf_tlb_flushID_SE) (u_int va);
74 void (*cf_tlb_flushD) (void);
75 void (*cf_tlb_flushD_SE) (u_int va);
80 * We define the following primitives:
82 * icache_sync_range Synchronize I-cache range
84 * dcache_wbinv_all Write-back and Invalidate D-cache
85 * dcache_wbinv_range Write-back and Invalidate D-cache range
86 * dcache_inv_range Invalidate D-cache range
87 * dcache_wb_range Write-back D-cache range
89 * idcache_wbinv_all Write-back and Invalidate D-cache,
91 * idcache_wbinv_range Write-back and Invalidate D-cache,
92 * Invalidate I-cache range
94 * Note that the ARM term for "write-back" is "clean". We use
95 * the term "write-back" since it's a more common way to describe
98 * There are some rules that must be followed:
100 * ID-cache Invalidate All:
101 * Unlike other functions, this one must never write back.
102 * It is used to intialize the MMU when it is in an unknown
103 * state (such as when it may have lines tagged as valid
104 * that belong to a previous set of mappings).
106 * I-cache Sync range:
107 * The goal is to synchronize the instruction stream,
108 * so you may beed to write-back dirty D-cache blocks
109 * first. If a range is requested, and you can't
110 * synchronize just a range, you have to hit the whole
113 * D-cache Write-Back and Invalidate range:
114 * If you can't WB-Inv a range, you must WB-Inv the
117 * D-cache Invalidate:
118 * If you can't Inv the D-cache, you must Write-Back
119 * and Invalidate. Code that uses this operation
120 * MUST NOT assume that the D-cache will not be written
123 * D-cache Write-Back:
124 * If you can't Write-back without doing an Inv,
125 * that's fine. Then treat this as a WB-Inv.
126 * Skipping the invalidate is merely an optimization.
129 * Valid virtual addresses must be passed to each
132 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
134 void (*cf_dcache_wbinv_all) (void);
135 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
136 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
137 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
139 void (*cf_idcache_inv_all) (void);
140 void (*cf_idcache_wbinv_all) (void);
141 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
143 void (*cf_l2cache_wbinv_all) (void);
144 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
145 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
146 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
147 void (*cf_l2cache_drain_writebuf) (void);
149 /* Other functions */
152 void (*cf_drain_writebuf) (void);
155 void (*cf_sleep) (int mode);
160 void (*cf_context_switch) (void);
163 void (*cf_setup) (void);
166 extern struct cpu_functions cpufuncs;
167 extern u_int cputype;
170 #define cpu_cpwait() cpufuncs.cf_cpwait()
172 #define cpu_control(c, e) cpufuncs.cf_control(c, e)
173 #define cpu_setttb(t) cpufuncs.cf_setttb(t)
175 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
176 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
177 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
178 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
180 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
182 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
183 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
184 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
185 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
187 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
188 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
189 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
192 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
193 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
194 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
195 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
196 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
199 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
201 #define cpu_sleep(m) cpufuncs.cf_sleep(m)
203 #define cpu_setup() cpufuncs.cf_setup()
205 int set_cpufuncs (void);
206 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
207 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
209 void cpufunc_nullop (void);
210 u_int cpu_ident (void);
211 u_int cpufunc_control (u_int clear, u_int bic);
212 void cpu_domains (u_int domains);
213 u_int cpu_faultstatus (void);
214 u_int cpu_faultaddress (void);
215 u_int cpu_get_control (void);
218 #if defined(CPU_FA526)
219 void fa526_setup (void);
220 void fa526_setttb (u_int ttb);
221 void fa526_context_switch (void);
222 void fa526_cpu_sleep (int);
223 void fa526_tlb_flushID_SE (u_int);
225 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
226 void fa526_dcache_wbinv_all (void);
227 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
228 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
229 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
230 void fa526_idcache_wbinv_all(void);
231 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
235 #if defined(CPU_ARM9) || defined(CPU_ARM9E)
236 void arm9_setttb (u_int);
237 void arm9_tlb_flushID_SE (u_int va);
238 void arm9_context_switch (void);
241 #if defined(CPU_ARM9)
242 void arm9_icache_sync_range (vm_offset_t, vm_size_t);
244 void arm9_dcache_wbinv_all (void);
245 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
246 void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
247 void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
249 void arm9_idcache_wbinv_all (void);
250 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
252 void arm9_setup (void);
254 extern unsigned arm9_dcache_sets_max;
255 extern unsigned arm9_dcache_sets_inc;
256 extern unsigned arm9_dcache_index_max;
257 extern unsigned arm9_dcache_index_inc;
260 #if defined(CPU_ARM9E)
261 void arm10_setup (void);
263 u_int sheeva_control_ext (u_int, u_int);
264 void sheeva_cpu_sleep (int);
265 void sheeva_setttb (u_int);
266 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
267 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
268 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
269 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
271 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
272 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
273 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
274 void sheeva_l2cache_wbinv_all (void);
277 #if defined(CPU_MV_PJ4B)
278 void armv6_idcache_wbinv_all (void);
280 #if defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || \
281 defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
282 void armv7_idcache_wbinv_all (void);
283 void armv7_cpu_sleep (int);
284 void armv7_setup (void);
285 void armv7_drain_writebuf (void);
287 void cortexa_setup (void);
289 #if defined(CPU_MV_PJ4B)
290 void pj4b_config (void);
291 void pj4bv7_setup (void);
294 #if defined(CPU_ARM1176)
295 void arm11_drain_writebuf (void);
297 void arm11x6_setup (void);
298 void arm11x6_sleep (int); /* no ref. for errata */
301 #if defined(CPU_ARM9E)
302 void armv5_ec_setttb(u_int);
304 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
306 void armv5_ec_dcache_wbinv_all(void);
307 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
308 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
309 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
311 void armv5_ec_idcache_wbinv_all(void);
312 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
315 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
316 defined(CPU_FA526) || \
317 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
318 defined(CPU_XSCALE_81342)
320 void armv4_tlb_flushID (void);
321 void armv4_tlb_flushD (void);
322 void armv4_tlb_flushD_SE (u_int va);
324 void armv4_drain_writebuf (void);
325 void armv4_idcache_inv_all (void);
328 #if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
329 defined(CPU_XSCALE_81342)
330 void xscale_cpwait (void);
332 void xscale_cpu_sleep (int mode);
334 u_int xscale_control (u_int clear, u_int bic);
336 void xscale_setttb (u_int ttb);
338 void xscale_tlb_flushID_SE (u_int va);
340 void xscale_cache_flushID (void);
341 void xscale_cache_flushI (void);
342 void xscale_cache_flushD (void);
343 void xscale_cache_flushD_SE (u_int entry);
345 void xscale_cache_cleanID (void);
346 void xscale_cache_cleanD (void);
347 void xscale_cache_cleanD_E (u_int entry);
349 void xscale_cache_clean_minidata (void);
351 void xscale_cache_purgeID (void);
352 void xscale_cache_purgeID_E (u_int entry);
353 void xscale_cache_purgeD (void);
354 void xscale_cache_purgeD_E (u_int entry);
356 void xscale_cache_syncI (void);
357 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
358 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
359 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
360 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
361 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
362 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
364 void xscale_context_switch (void);
366 void xscale_setup (void);
367 #endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
369 #ifdef CPU_XSCALE_81342
371 void xscalec3_l2cache_purge (void);
372 void xscalec3_cache_purgeID (void);
373 void xscalec3_cache_purgeD (void);
374 void xscalec3_cache_cleanID (void);
375 void xscalec3_cache_cleanD (void);
376 void xscalec3_cache_syncI (void);
378 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
379 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
380 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
381 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
382 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
384 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
385 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
386 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
389 void xscalec3_setttb (u_int ttb);
390 void xscalec3_context_switch (void);
392 #endif /* CPU_XSCALE_81342 */
395 * Macros for manipulating CPU interrupts
398 #define __ARM_INTR_BITS (PSR_I | PSR_F)
400 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A)
403 static __inline uint32_t
404 __set_cpsr(uint32_t bic, uint32_t eor)
409 "mrs %0, cpsr\n" /* Get the CPSR */
410 "bic %1, %0, %2\n" /* Clear bits */
411 "eor %1, %1, %3\n" /* XOR bits */
412 "msr cpsr_xc, %1\n" /* Set the CPSR */
413 : "=&r" (ret), "=&r" (tmp)
414 : "r" (bic), "r" (eor) : "memory");
419 static __inline uint32_t
420 disable_interrupts(uint32_t mask)
423 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
426 static __inline uint32_t
427 enable_interrupts(uint32_t mask)
430 return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
433 static __inline uint32_t
434 restore_interrupts(uint32_t old_cpsr)
437 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
440 static __inline register_t
444 return (disable_interrupts(PSR_I | PSR_F));
448 intr_restore(register_t s)
451 restore_interrupts(s);
453 #undef __ARM_INTR_BITS
456 * Functions to manipulate cpu r13
457 * (in arm/arm32/setstack.S)
460 void set_stackptr (u_int mode, u_int address);
461 u_int get_stackptr (u_int mode);
467 int get_pc_str_offset (void);
470 * CPU functions from locore.S
473 void cpu_reset (void) __attribute__((__noreturn__));
476 * Cache info variables.
479 /* PRIMARY CACHE VARIABLES */
480 extern int arm_picache_size;
481 extern int arm_picache_line_size;
482 extern int arm_picache_ways;
484 extern int arm_pdcache_size; /* and unified */
485 extern int arm_pdcache_line_size;
486 extern int arm_pdcache_ways;
488 extern int arm_pcache_type;
489 extern int arm_pcache_unified;
491 extern int arm_dcache_align;
492 extern int arm_dcache_align_mask;
494 extern u_int arm_cache_level;
495 extern u_int arm_cache_loc;
496 extern u_int arm_cache_type[14];
499 #endif /* _MACHINE_CPUFUNC_H_ */
501 /* End of cpufunc.h */