1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
4 * Copyright (c) 1997 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Prototypes for cpu, mmu and tlb related functions.
44 #ifndef _MACHINE_CPUFUNC_H_
45 #define _MACHINE_CPUFUNC_H_
49 #include <sys/types.h>
50 #include <machine/armreg.h>
55 __asm(".word 0xe7ffffff");
58 struct cpu_functions {
62 void (*cf_cpwait) (void);
66 u_int (*cf_control) (u_int bic, u_int eor);
67 void (*cf_setttb) (u_int ttb);
71 void (*cf_tlb_flushID) (void);
72 void (*cf_tlb_flushID_SE) (u_int va);
73 void (*cf_tlb_flushD) (void);
74 void (*cf_tlb_flushD_SE) (u_int va);
79 * We define the following primitives:
81 * icache_sync_range Synchronize I-cache range
83 * dcache_wbinv_all Write-back and Invalidate D-cache
84 * dcache_wbinv_range Write-back and Invalidate D-cache range
85 * dcache_inv_range Invalidate D-cache range
86 * dcache_wb_range Write-back D-cache range
88 * idcache_wbinv_all Write-back and Invalidate D-cache,
90 * idcache_wbinv_range Write-back and Invalidate D-cache,
91 * Invalidate I-cache range
93 * Note that the ARM term for "write-back" is "clean". We use
94 * the term "write-back" since it's a more common way to describe
97 * There are some rules that must be followed:
99 * ID-cache Invalidate All:
100 * Unlike other functions, this one must never write back.
101 * It is used to intialize the MMU when it is in an unknown
102 * state (such as when it may have lines tagged as valid
103 * that belong to a previous set of mappings).
105 * I-cache Sync range:
106 * The goal is to synchronize the instruction stream,
107 * so you may beed to write-back dirty D-cache blocks
108 * first. If a range is requested, and you can't
109 * synchronize just a range, you have to hit the whole
112 * D-cache Write-Back and Invalidate range:
113 * If you can't WB-Inv a range, you must WB-Inv the
116 * D-cache Invalidate:
117 * If you can't Inv the D-cache, you must Write-Back
118 * and Invalidate. Code that uses this operation
119 * MUST NOT assume that the D-cache will not be written
122 * D-cache Write-Back:
123 * If you can't Write-back without doing an Inv,
124 * that's fine. Then treat this as a WB-Inv.
125 * Skipping the invalidate is merely an optimization.
128 * Valid virtual addresses must be passed to each
131 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
133 void (*cf_dcache_wbinv_all) (void);
134 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
135 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
136 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
138 void (*cf_idcache_inv_all) (void);
139 void (*cf_idcache_wbinv_all) (void);
140 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
142 void (*cf_l2cache_wbinv_all) (void);
143 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
144 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
145 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
146 void (*cf_l2cache_drain_writebuf) (void);
148 /* Other functions */
151 void (*cf_drain_writebuf) (void);
154 void (*cf_sleep) (int mode);
159 void (*cf_context_switch) (void);
162 void (*cf_setup) (void);
165 extern struct cpu_functions cpufuncs;
166 extern u_int cputype;
169 #define cpu_cpwait() cpufuncs.cf_cpwait()
171 #define cpu_control(c, e) cpufuncs.cf_control(c, e)
172 #define cpu_setttb(t) cpufuncs.cf_setttb(t)
174 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
175 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
176 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
177 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
179 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
181 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
182 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
183 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
184 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
186 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
187 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
188 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
191 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
192 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
193 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
194 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
195 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
198 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
200 #define cpu_sleep(m) cpufuncs.cf_sleep(m)
202 #define cpu_setup() cpufuncs.cf_setup()
204 int set_cpufuncs (void);
205 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
206 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
208 void cpufunc_nullop (void);
209 u_int cpu_ident (void);
210 u_int cpufunc_control (u_int clear, u_int bic);
211 void cpu_domains (u_int domains);
212 u_int cpu_faultstatus (void);
213 u_int cpu_faultaddress (void);
214 u_int cpu_get_control (void);
217 #if defined(CPU_FA526)
218 void fa526_setup (void);
219 void fa526_setttb (u_int ttb);
220 void fa526_context_switch (void);
221 void fa526_cpu_sleep (int);
222 void fa526_tlb_flushID_SE (u_int);
224 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
225 void fa526_dcache_wbinv_all (void);
226 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
227 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
228 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
229 void fa526_idcache_wbinv_all(void);
230 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
234 #if defined(CPU_ARM9) || defined(CPU_ARM9E)
235 void arm9_setttb (u_int);
236 void arm9_tlb_flushID_SE (u_int va);
237 void arm9_context_switch (void);
240 #if defined(CPU_ARM9)
241 void arm9_icache_sync_range (vm_offset_t, vm_size_t);
243 void arm9_dcache_wbinv_all (void);
244 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
245 void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
246 void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
248 void arm9_idcache_wbinv_all (void);
249 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
251 void arm9_setup (void);
253 extern unsigned arm9_dcache_sets_max;
254 extern unsigned arm9_dcache_sets_inc;
255 extern unsigned arm9_dcache_index_max;
256 extern unsigned arm9_dcache_index_inc;
259 #if defined(CPU_ARM9E)
260 void arm10_setup (void);
262 u_int sheeva_control_ext (u_int, u_int);
263 void sheeva_cpu_sleep (int);
264 void sheeva_setttb (u_int);
265 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
266 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
267 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
268 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
270 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
271 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
272 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
273 void sheeva_l2cache_wbinv_all (void);
276 #if defined(CPU_MV_PJ4B)
277 void armv6_idcache_wbinv_all (void);
279 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
280 void armv7_idcache_wbinv_all (void);
281 void armv7_cpu_sleep (int);
282 void armv7_setup (void);
283 void armv7_drain_writebuf (void);
285 void cortexa_setup (void);
287 #if defined(CPU_MV_PJ4B)
288 void pj4b_config (void);
289 void pj4bv7_setup (void);
292 #if defined(CPU_ARM1176)
293 void arm11_drain_writebuf (void);
295 void arm11x6_setup (void);
296 void arm11x6_sleep (int); /* no ref. for errata */
299 #if defined(CPU_ARM9E)
300 void armv5_ec_setttb(u_int);
302 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
304 void armv5_ec_dcache_wbinv_all(void);
305 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
306 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
307 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
309 void armv5_ec_idcache_wbinv_all(void);
310 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
313 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
314 defined(CPU_FA526) || \
315 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
316 defined(CPU_XSCALE_81342)
318 void armv4_tlb_flushID (void);
319 void armv4_tlb_flushD (void);
320 void armv4_tlb_flushD_SE (u_int va);
322 void armv4_drain_writebuf (void);
323 void armv4_idcache_inv_all (void);
326 #if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
327 defined(CPU_XSCALE_81342)
328 void xscale_cpwait (void);
330 void xscale_cpu_sleep (int mode);
332 u_int xscale_control (u_int clear, u_int bic);
334 void xscale_setttb (u_int ttb);
336 void xscale_tlb_flushID_SE (u_int va);
338 void xscale_cache_flushID (void);
339 void xscale_cache_flushI (void);
340 void xscale_cache_flushD (void);
341 void xscale_cache_flushD_SE (u_int entry);
343 void xscale_cache_cleanID (void);
344 void xscale_cache_cleanD (void);
345 void xscale_cache_cleanD_E (u_int entry);
347 void xscale_cache_clean_minidata (void);
349 void xscale_cache_purgeID (void);
350 void xscale_cache_purgeID_E (u_int entry);
351 void xscale_cache_purgeD (void);
352 void xscale_cache_purgeD_E (u_int entry);
354 void xscale_cache_syncI (void);
355 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
356 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
357 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
358 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
359 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
360 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
362 void xscale_context_switch (void);
364 void xscale_setup (void);
365 #endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
367 #ifdef CPU_XSCALE_81342
369 void xscalec3_l2cache_purge (void);
370 void xscalec3_cache_purgeID (void);
371 void xscalec3_cache_purgeD (void);
372 void xscalec3_cache_cleanID (void);
373 void xscalec3_cache_cleanD (void);
374 void xscalec3_cache_syncI (void);
376 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
377 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
378 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
379 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
380 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
382 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
383 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
384 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
387 void xscalec3_setttb (u_int ttb);
388 void xscalec3_context_switch (void);
390 #endif /* CPU_XSCALE_81342 */
393 * Macros for manipulating CPU interrupts
396 #define __ARM_INTR_BITS (PSR_I | PSR_F)
398 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A)
401 static __inline uint32_t
402 __set_cpsr(uint32_t bic, uint32_t eor)
407 "mrs %0, cpsr\n" /* Get the CPSR */
408 "bic %1, %0, %2\n" /* Clear bits */
409 "eor %1, %1, %3\n" /* XOR bits */
410 "msr cpsr_xc, %1\n" /* Set the CPSR */
411 : "=&r" (ret), "=&r" (tmp)
412 : "r" (bic), "r" (eor) : "memory");
417 static __inline uint32_t
418 disable_interrupts(uint32_t mask)
421 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
424 static __inline uint32_t
425 enable_interrupts(uint32_t mask)
428 return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
431 static __inline uint32_t
432 restore_interrupts(uint32_t old_cpsr)
435 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
438 static __inline register_t
442 return (disable_interrupts(PSR_I | PSR_F));
446 intr_restore(register_t s)
449 restore_interrupts(s);
451 #undef __ARM_INTR_BITS
454 * Functions to manipulate cpu r13
455 * (in arm/arm32/setstack.S)
458 void set_stackptr (u_int mode, u_int address);
459 u_int get_stackptr (u_int mode);
465 int get_pc_str_offset (void);
468 * CPU functions from locore.S
471 void cpu_reset (void) __attribute__((__noreturn__));
474 * Cache info variables.
477 /* PRIMARY CACHE VARIABLES */
478 extern int arm_picache_size;
479 extern int arm_picache_line_size;
480 extern int arm_picache_ways;
482 extern int arm_pdcache_size; /* and unified */
483 extern int arm_pdcache_line_size;
484 extern int arm_pdcache_ways;
486 extern int arm_pcache_type;
487 extern int arm_pcache_unified;
489 extern int arm_dcache_align;
490 extern int arm_dcache_align_mask;
492 extern u_int arm_cache_level;
493 extern u_int arm_cache_loc;
494 extern u_int arm_cache_type[14];
497 #endif /* _MACHINE_CPUFUNC_H_ */
499 /* End of cpufunc.h */