1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
4 * SPDX-License-Identifier: BSD-4-Clause
6 * Copyright (c) 1997 Mark Brinicombe.
7 * Copyright (c) 1997 Causality Limited
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Causality Limited.
21 * 4. The name of Causality Limited may not be used to endorse or promote
22 * products derived from this software without specific prior written
25 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * RiscBSD kernel project
41 * Prototypes for cpu, mmu and tlb related functions.
46 #ifndef _MACHINE_CPUFUNC_H_
47 #define _MACHINE_CPUFUNC_H_
51 #include <sys/types.h>
52 #include <machine/armreg.h>
60 struct cpu_functions {
64 void (*cf_cpwait) (void);
68 u_int (*cf_control) (u_int bic, u_int eor);
69 void (*cf_setttb) (u_int ttb);
73 void (*cf_tlb_flushID) (void);
74 void (*cf_tlb_flushID_SE) (u_int va);
75 void (*cf_tlb_flushD) (void);
76 void (*cf_tlb_flushD_SE) (u_int va);
81 * We define the following primitives:
83 * icache_sync_range Synchronize I-cache range
85 * dcache_wbinv_all Write-back and Invalidate D-cache
86 * dcache_wbinv_range Write-back and Invalidate D-cache range
87 * dcache_inv_range Invalidate D-cache range
88 * dcache_wb_range Write-back D-cache range
90 * idcache_wbinv_all Write-back and Invalidate D-cache,
92 * idcache_wbinv_range Write-back and Invalidate D-cache,
93 * Invalidate I-cache range
95 * Note that the ARM term for "write-back" is "clean". We use
96 * the term "write-back" since it's a more common way to describe
99 * There are some rules that must be followed:
101 * ID-cache Invalidate All:
102 * Unlike other functions, this one must never write back.
103 * It is used to intialize the MMU when it is in an unknown
104 * state (such as when it may have lines tagged as valid
105 * that belong to a previous set of mappings).
107 * I-cache Sync range:
108 * The goal is to synchronize the instruction stream,
109 * so you may beed to write-back dirty D-cache blocks
110 * first. If a range is requested, and you can't
111 * synchronize just a range, you have to hit the whole
114 * D-cache Write-Back and Invalidate range:
115 * If you can't WB-Inv a range, you must WB-Inv the
118 * D-cache Invalidate:
119 * If you can't Inv the D-cache, you must Write-Back
120 * and Invalidate. Code that uses this operation
121 * MUST NOT assume that the D-cache will not be written
124 * D-cache Write-Back:
125 * If you can't Write-back without doing an Inv,
126 * that's fine. Then treat this as a WB-Inv.
127 * Skipping the invalidate is merely an optimization.
130 * Valid virtual addresses must be passed to each
133 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
135 void (*cf_dcache_wbinv_all) (void);
136 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
137 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
138 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
140 void (*cf_idcache_inv_all) (void);
141 void (*cf_idcache_wbinv_all) (void);
142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
144 void (*cf_l2cache_wbinv_all) (void);
145 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
146 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
147 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
148 void (*cf_l2cache_drain_writebuf) (void);
150 /* Other functions */
153 void (*cf_drain_writebuf) (void);
156 void (*cf_sleep) (int mode);
161 void (*cf_context_switch) (void);
164 void (*cf_setup) (void);
167 extern struct cpu_functions cpufuncs;
168 extern u_int cputype;
171 #define cpu_cpwait() cpufuncs.cf_cpwait()
173 #define cpu_control(c, e) cpufuncs.cf_control(c, e)
174 #define cpu_setttb(t) cpufuncs.cf_setttb(t)
176 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
177 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
178 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
179 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
181 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
183 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
184 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
185 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
186 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
188 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
189 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
190 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
193 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
194 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
195 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
196 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
197 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
200 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
202 #define cpu_sleep(m) cpufuncs.cf_sleep(m)
204 #define cpu_setup() cpufuncs.cf_setup()
206 int set_cpufuncs (void);
207 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
208 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
210 void cpufunc_nullop (void);
211 u_int cpufunc_control (u_int clear, u_int bic);
212 void cpu_domains (u_int domains);
215 #if defined(CPU_ARM9E)
216 void arm9_tlb_flushID_SE (u_int va);
217 void arm9_context_switch (void);
219 u_int sheeva_control_ext (u_int, u_int);
220 void sheeva_cpu_sleep (int);
221 void sheeva_setttb (u_int);
222 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
223 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
224 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
225 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
227 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
228 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
229 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
230 void sheeva_l2cache_wbinv_all (void);
233 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
234 void armv7_cpu_sleep (int);
236 #if defined(CPU_MV_PJ4B)
237 void pj4b_config (void);
240 #if defined(CPU_ARM1176)
241 void arm11x6_sleep (int); /* no ref. for errata */
244 #if defined(CPU_ARM9E)
245 void armv5_ec_setttb(u_int);
247 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
249 void armv5_ec_dcache_wbinv_all(void);
250 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
251 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
252 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
254 void armv5_ec_idcache_wbinv_all(void);
255 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
257 void armv4_tlb_flushID (void);
258 void armv4_tlb_flushD (void);
259 void armv4_tlb_flushD_SE (u_int va);
261 void armv4_drain_writebuf (void);
262 void armv4_idcache_inv_all (void);
266 * Macros for manipulating CPU interrupts
269 #define __ARM_INTR_BITS (PSR_I | PSR_F)
271 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A)
274 static __inline uint32_t
275 __set_cpsr(uint32_t bic, uint32_t eor)
280 "mrs %0, cpsr\n" /* Get the CPSR */
281 "bic %1, %0, %2\n" /* Clear bits */
282 "eor %1, %1, %3\n" /* XOR bits */
283 "msr cpsr_xc, %1\n" /* Set the CPSR */
284 : "=&r" (ret), "=&r" (tmp)
285 : "r" (bic), "r" (eor) : "memory");
290 static __inline uint32_t
291 disable_interrupts(uint32_t mask)
294 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
297 static __inline uint32_t
298 enable_interrupts(uint32_t mask)
301 return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
304 static __inline uint32_t
305 restore_interrupts(uint32_t old_cpsr)
308 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
311 static __inline register_t
315 return (disable_interrupts(PSR_I | PSR_F));
319 intr_restore(register_t s)
322 restore_interrupts(s);
324 #undef __ARM_INTR_BITS
327 * Functions to manipulate cpu r13
328 * (in arm/arm32/setstack.S)
331 void set_stackptr (u_int mode, u_int address);
332 u_int get_stackptr (u_int mode);
335 * CPU functions from locore.S
338 void cpu_reset (void) __attribute__((__noreturn__));
341 * Cache info variables.
344 /* PRIMARY CACHE VARIABLES */
345 extern int arm_picache_size;
346 extern int arm_picache_line_size;
347 extern int arm_picache_ways;
349 extern int arm_pdcache_size; /* and unified */
350 extern int arm_pdcache_line_size;
351 extern int arm_pdcache_ways;
353 extern int arm_pcache_type;
354 extern int arm_pcache_unified;
356 extern int arm_dcache_align;
357 extern int arm_dcache_align_mask;
359 extern u_int arm_cache_level;
360 extern u_int arm_cache_loc;
361 extern u_int arm_cache_type[14];
370 * This matches the instruction used by GDB for software
377 #endif /* _MACHINE_CPUFUNC_H_ */
379 /* End of cpufunc.h */