2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_CPUINFO_H_
31 #define _MACHINE_CPUINFO_H_
33 #include <sys/types.h>
35 #define CPU_IMPLEMENTER_ARM 0x41
36 #define CPU_IMPLEMENTER_QCOM 0x51
37 #define CPU_IMPLEMENTER_MRVL 0x56
40 #define CPU_ARCH_ARM1176 0xB76
41 #define CPU_ARCH_CORTEX_A5 0xC05
42 #define CPU_ARCH_CORTEX_A7 0xC07
43 #define CPU_ARCH_CORTEX_A8 0xC08
44 #define CPU_ARCH_CORTEX_A9 0xC09
45 #define CPU_ARCH_CORTEX_A12 0xC0D
46 #define CPU_ARCH_CORTEX_A15 0xC0F
47 #define CPU_ARCH_CORTEX_A17 0xC11
48 #define CPU_ARCH_CORTEX_A53 0xD03
49 #define CPU_ARCH_CORTEX_A57 0xD07
50 #define CPU_ARCH_CORTEX_A72 0xD08
51 #define CPU_ARCH_CORTEX_A73 0xD09
52 #define CPU_ARCH_CORTEX_A75 0xD0A
55 #define CPU_ARCH_KRAIT_300 0x06F
58 #define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */
59 #define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */
62 /* raw id registers */
87 /* Parsed bits of above registers... */
97 int outermost_shareability;
98 int shareability_levels;
99 int auxiliary_registers;
100 int innermost_shareability;
107 int maintenance_broadcast;
110 int generic_timer_ext;
111 int virtualization_ext;
115 int dcache_line_size;
116 int dcache_line_mask;
117 int icache_line_size;
118 int icache_line_mask;
124 extern struct cpuinfo cpuinfo;
126 void cpuinfo_init(void);
127 void cpuinfo_init_bp_hardening(void);
128 void cpuinfo_reinit_mmu(uint32_t ttb);
129 #endif /* _MACHINE_CPUINFO_H_ */