2 * Copyright (c) 2001 David E. O'Brien
3 * Copyright (c) 1990 The Regents of the University of California.
6 * This code is derived from software contributed to Berkeley by
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10 * modification, are permitted provided that the following conditions
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18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
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37 * from: @(#)param.h 5.8 (Berkeley) 6/28/91
41 #ifndef _ARM_INCLUDE_PARAM_H_
42 #define _ARM_INCLUDE_PARAM_H_
45 * Machine dependent constants for StrongARM
48 #include <machine/_align.h>
50 #define STACKALIGNBYTES (8 - 1)
51 #define STACKALIGN(p) ((u_int)(p) & ~STACKALIGNBYTES)
53 #define __PCI_REROUTE_INTERRUPT
56 #define _V6_SUFFIX "v6"
61 #ifdef __ARM_BIG_ENDIAN
62 #define _EB_SUFFIX "eb"
71 #define MACHINE_ARCH "arm" _V6_SUFFIX _EB_SUFFIX
74 #if defined(SMP) || defined(KLD_MODULE)
80 #endif /* SMP || KLD_MODULE */
86 #define ALIGNBYTES _ALIGNBYTES
87 #define ALIGN(p) _ALIGN(p)
89 * ALIGNED_POINTER is a boolean macro that checks whether an address
90 * is valid to fetch data elements of type t from on this architecture.
91 * This does not reflect the optimal alignment, just the possibility
92 * (within reasonable limits).
94 * armv4 and v5 require alignment to the type's size. armv6 requires 8-byte
95 * alignment for the ldrd/strd instructions, but otherwise follows armv7 rules.
96 * armv7 requires that an 8-byte type be aligned to at least a 4-byte boundary;
97 * access to smaller types can be unaligned, except that the compiler may
98 * optimize access to adjacent uint32_t values into a single load/store-multiple
99 * instruction which requires 4-byte alignment, so we must provide the most-
100 * pessimistic answer possible even on armv7.
102 #define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t)-1)) == 0)
105 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
106 * architecture. It should be used with appropriate caution.
108 #define CACHE_LINE_SHIFT 6
109 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
111 #define PAGE_SHIFT 12
112 #define PAGE_SIZE (1 << PAGE_SHIFT) /* Page size */
113 #define PAGE_MASK (PAGE_SIZE - 1)
115 #define PDR_SHIFT 20 /* log2(NBPDR) */
116 #define NBPDR (1 << PDR_SHIFT)
117 #define PDRMASK (NBPDR - 1)
118 #define NPDEPG (1 << (32 - PDR_SHIFT))
120 #define MAXPAGESIZES 2 /* maximum number of supported page sizes */
123 #define KSTACK_PAGES 2
124 #endif /* !KSTACK_PAGES */
126 #ifndef FPCONTEXTSIZE
127 #define FPCONTEXTSIZE (0x100)
130 #ifndef KSTACK_GUARD_PAGES
131 #define KSTACK_GUARD_PAGES 1
132 #endif /* !KSTACK_GUARD_PAGES */
134 #define USPACE_SVC_STACK_TOP (kstack_pages * PAGE_SIZE)
137 * Mach derived conversion macros
139 #define trunc_page(x) ((x) & ~PAGE_MASK)
140 #define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK)
141 #define trunc_1mpage(x) ((unsigned)(x) & ~PDRMASK)
142 #define round_1mpage(x) ((((unsigned)(x)) + PDRMASK) & ~PDRMASK)
144 #define atop(x) ((unsigned)(x) >> PAGE_SHIFT)
145 #define ptoa(x) ((unsigned)(x) << PAGE_SHIFT)
147 #define arm32_btop(x) ((unsigned)(x) >> PAGE_SHIFT)
148 #define arm32_ptob(x) ((unsigned)(x) << PAGE_SHIFT)
150 #define pgtok(x) ((x) * (PAGE_SIZE / 1024))
152 #endif /* !_ARM_INCLUDE_PARAM_H_ */