2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2001 David E. O'Brien
5 * Copyright (c) 1990 The Regents of the University of California.
8 * This code is derived from software contributed to Berkeley by
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20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
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39 * from: @(#)param.h 5.8 (Berkeley) 6/28/91
43 #ifndef _ARM_INCLUDE_PARAM_H_
44 #define _ARM_INCLUDE_PARAM_H_
47 * Machine dependent constants for StrongARM
50 #include <machine/_align.h>
52 #define STACKALIGNBYTES (8 - 1)
53 #define STACKALIGN(p) ((u_int)(p) & ~STACKALIGNBYTES)
55 #define __PCI_REROUTE_INTERRUPT
58 #define _V_SUFFIX "v7"
60 #define _V_SUFFIX "v6"
65 #ifdef __ARM_BIG_ENDIAN
66 #define _EB_SUFFIX "eb"
75 #define MACHINE_ARCH "arm" _V_SUFFIX _EB_SUFFIX
78 #if defined(SMP) || defined(KLD_MODULE)
84 #endif /* SMP || KLD_MODULE */
90 #define ALIGNBYTES _ALIGNBYTES
91 #define ALIGN(p) _ALIGN(p)
93 * ALIGNED_POINTER is a boolean macro that checks whether an address
94 * is valid to fetch data elements of type t from on this architecture.
95 * This does not reflect the optimal alignment, just the possibility
96 * (within reasonable limits).
98 * armv4 and v5 require alignment to the type's size. armv6 requires 8-byte
99 * alignment for the ldrd/strd instructions, but otherwise follows armv7 rules.
100 * armv7 requires that an 8-byte type be aligned to at least a 4-byte boundary;
101 * access to smaller types can be unaligned, except that the compiler may
102 * optimize access to adjacent uint32_t values into a single load/store-multiple
103 * instruction which requires 4-byte alignment, so we must provide the most-
104 * pessimistic answer possible even on armv7.
106 #define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t)-1)) == 0)
109 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
110 * architecture. It should be used with appropriate caution.
112 #define CACHE_LINE_SHIFT 6
113 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
115 #define PAGE_SHIFT 12
116 #define PAGE_SIZE (1 << PAGE_SHIFT) /* Page size */
117 #define PAGE_MASK (PAGE_SIZE - 1)
119 #define PDR_SHIFT 20 /* log2(NBPDR) */
120 #define NBPDR (1 << PDR_SHIFT)
121 #define PDRMASK (NBPDR - 1)
122 #define NPDEPG (1 << (32 - PDR_SHIFT))
124 #define MAXPAGESIZES 2 /* maximum number of supported page sizes */
127 #define KSTACK_PAGES 2
128 #endif /* !KSTACK_PAGES */
130 #ifndef FPCONTEXTSIZE
131 #define FPCONTEXTSIZE (0x100)
134 #ifndef KSTACK_GUARD_PAGES
135 #define KSTACK_GUARD_PAGES 1
136 #endif /* !KSTACK_GUARD_PAGES */
138 #define USPACE_SVC_STACK_TOP (kstack_pages * PAGE_SIZE)
141 * Mach derived conversion macros
143 #define trunc_page(x) ((x) & ~PAGE_MASK)
144 #define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK)
145 #define trunc_1mpage(x) ((unsigned)(x) & ~PDRMASK)
146 #define round_1mpage(x) ((((unsigned)(x)) + PDRMASK) & ~PDRMASK)
148 #define atop(x) ((unsigned)(x) >> PAGE_SHIFT)
149 #define ptoa(x) ((unsigned)(x) << PAGE_SHIFT)
151 #define arm32_btop(x) ((unsigned)(x) >> PAGE_SHIFT)
152 #define arm32_ptob(x) ((unsigned)(x) << PAGE_SHIFT)
154 #define pgtok(x) ((x) * (PAGE_SIZE / 1024))
156 #endif /* !_ARM_INCLUDE_PARAM_H_ */