2 * Copyright (c) 2012 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * PL310 - L2 Cache Controller register offsets.
37 #define PL310_CACHE_ID 0x000
38 #define CACHE_ID_RELEASE_SHIFT 0
39 #define CACHE_ID_RELEASE_MASK 0x3f
40 #define CACHE_ID_RELEASE_r0p0 0x00
41 #define CACHE_ID_RELEASE_r1p0 0x02
42 #define CACHE_ID_RELEASE_r2p0 0x04
43 #define CACHE_ID_RELEASE_r3p0 0x05
44 #define CACHE_ID_RELEASE_r3p1 0x06
45 #define CACHE_ID_RELEASE_r3p2 0x08
46 #define CACHE_ID_RELEASE_r3p3 0x09
47 #define CACHE_ID_PARTNUM_SHIFT 6
48 #define CACHE_ID_PARTNUM_MASK 0xf
49 #define CACHE_ID_PARTNUM_VALUE 0x3
50 #define PL310_CACHE_TYPE 0x004
51 #define PL310_CTRL 0x100
52 #define CTRL_ENABLED 0x01
53 #define CTRL_DISABLED 0x00
54 #define PL310_AUX_CTRL 0x104
55 #define AUX_CTRL_MASK 0xc0000fff
56 #define AUX_CTRL_ASSOCIATIVITY_SHIFT 16
57 #define AUX_CTRL_WAY_SIZE_SHIFT 17
58 #define AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
59 #define AUX_CTRL_SHARE_OVERRIDE (1 << 22)
60 #define AUX_CTRL_NS_LOCKDOWN (1 << 26)
61 #define AUX_CTRL_NS_INT_CTRL (1 << 27)
62 #define AUX_CTRL_DATA_PREFETCH (1 << 28)
63 #define AUX_CTRL_INSTR_PREFETCH (1 << 29)
64 #define AUX_CTRL_EARLY_BRESP (1 << 30)
65 #define PL310_EVENT_COUNTER_CTRL 0x200
66 #define EVENT_COUNTER_CTRL_ENABLED (1 << 0)
67 #define EVENT_COUNTER_CTRL_C0_RESET (1 << 1)
68 #define EVENT_COUNTER_CTRL_C1_RESET (1 << 2)
69 #define PL310_EVENT_COUNTER1_CONF 0x204
70 #define PL310_EVENT_COUNTER0_CONF 0x208
71 #define EVENT_COUNTER_CONF_NOINTR 0
72 #define EVENT_COUNTER_CONF_INCR 1
73 #define EVENT_COUNTER_CONF_OVFW 2
74 #define EVENT_COUNTER_CONF_NOEV (0 << 2)
75 #define EVENT_COUNTER_CONF_CO (1 << 2)
76 #define EVENT_COUNTER_CONF_DRHIT (2 << 2)
77 #define EVENT_COUNTER_CONF_DRREQ (3 << 2)
78 #define EVENT_COUNTER_CONF_DWHIT (4 << 2)
79 #define EVENT_COUNTER_CONF_DWREQ (5 << 2)
80 #define EVENT_COUNTER_CONF_DWTREQ (6 << 2)
81 #define EVENT_COUNTER_CONF_DIRHIT (7 << 2)
82 #define EVENT_COUNTER_CONF_DIRREQ (8 << 2)
83 #define EVENT_COUNTER_CONF_WA (9 << 2)
84 #define PL310_EVENT_COUNTER1_VAL 0x20C
85 #define PL310_EVENT_COUNTER0_VAL 0x210
86 #define PL310_INTR_MASK 0x214
87 #define PL310_MASKED_INTR_STAT 0x218
88 #define PL310_RAW_INTR_STAT 0x21C
89 #define PL310_INTR_CLEAR 0x220
90 #define INTR_MASK_ALL ((1 << 9) - 1)
91 #define INTR_MASK_ECNTR (1 << 0)
92 #define INTR_MASK_PARRT (1 << 1)
93 #define INTR_MASK_PARRD (1 << 2)
94 #define INTR_MASK_ERRWT (1 << 3)
95 #define INTR_MASK_ERRWD (1 << 4)
96 #define INTR_MASK_ERRRT (1 << 5)
97 #define INTR_MASK_ERRRD (1 << 6)
98 #define INTR_MASK_SLVERR (1 << 7)
99 #define INTR_MASK_DECERR (1 << 8)
100 #define PL310_CACHE_SYNC 0x730
101 #define PL310_INV_LINE_PA 0x770
102 #define PL310_INV_WAY 0x77C
103 #define PL310_CLEAN_LINE_PA 0x7B0
104 #define PL310_CLEAN_LINE_IDX 0x7B8
105 #define PL310_CLEAN_WAY 0x7BC
106 #define PL310_CLEAN_INV_LINE_PA 0x7F0
107 #define PL310_CLEAN_INV_LINE_IDX 0x7F8
108 #define PL310_CLEAN_INV_WAY 0x7FC
109 #define PL310_LOCKDOWN_D_WAY(x) (0x900 + ((x) * 8))
110 #define PL310_LOCKDOWN_I_WAY(x) (0x904 + ((x) * 8))
111 #define PL310_LOCKDOWN_LINE_ENABLE 0x950
112 #define PL310_UNLOCK_ALL_LINES_WAY 0x954
113 #define PL310_ADDR_FILTER_STAR 0xC00
114 #define PL310_ADDR_FILTER_END 0xC04
115 #define PL310_DEBUG_CTRL 0xF40
116 #define PL310_PREFETCH_CTRL 0xF60
117 #define PREFETCH_CTRL_OFFSET_MASK (0x1f)
118 #define PREFETCH_CTRL_NOTSAMEID (1 << 21)
119 #define PREFETCH_CTRL_INCR_DL (1 << 23)
120 #define PREFETCH_CTRL_PREFETCH_DROP (1 << 24)
121 #define PREFETCH_CTRL_DL_ON_WRAP (1 << 27)
122 #define PREFETCH_CTRL_DATA_PREFETCH (1 << 28)
123 #define PREFETCH_CTRL_INSTR_PREFETCH (1 << 29)
124 #define PREFETCH_CTRL_DL (1 << 30)
125 #define PL310_POWER_CTRL 0xF60
129 struct resource *sc_mem_res;
130 struct resource *sc_irq_res;
134 u_int sc_rtl_revision;
138 * pl310_read4 - read a 32-bit value from the PL310 registers
139 * pl310_write4 - write a 32-bit value from the PL310 registers
140 * @off: byte offset within the register set to read from
141 * @val: the value to write into the register
148 * nothing in case of write function, if read function returns the value read.
150 static __inline uint32_t
151 pl310_read4(struct pl310_softc *sc, bus_size_t off)
154 return bus_read_4(sc->sc_mem_res, off);
158 pl310_write4(struct pl310_softc *sc, bus_size_t off, uint32_t val)
161 bus_write_4(sc->sc_mem_res, off, val);
164 void platform_pl310_init(struct pl310_softc *);
165 void platform_pl310_write_ctrl(struct pl310_softc *, uint32_t);
166 void platform_pl310_write_debug(struct pl310_softc *, uint32_t);
168 #endif /* PL310_H_ */