2 * Copyright (c) 1991 Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * the Systems Programming Group of the University of Utah Computer
7 * Science Department and William Jolitz of UUNET Technologies Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * Derived from hp300 version by Mike Hibler, this version by William
38 * Jolitz uses a recursive map [a pde points to the page directory] to
39 * map the page tables using the pagetables themselves. This is done to
40 * reduce the impact on kernel virtual memory for lots of sparse address
41 * space, and to reduce the cost of memory to each process.
43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
50 #ifndef _MACHINE_PMAP_H_
51 #define _MACHINE_PMAP_H_
53 #include <machine/pte.h>
54 #include <machine/cpuconf.h>
58 #if ARM_ARCH_6 || ARM_ARCH_7A
66 #define PTE_PAGETABLE 6
70 #define PTE_PAGETABLE 3
85 #include <sys/queue.h>
86 #include <sys/_cpuset.h>
87 #include <sys/_lock.h>
88 #include <sys/_mutex.h>
90 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */
91 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */
95 #define vtophys(va) pmap_kextract((vm_offset_t)(va))
99 #define pmap_page_get_memattr(m) ((m)->md.pv_memattr)
100 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
101 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
102 boolean_t pmap_page_is_mapped(vm_page_t);
104 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
106 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
113 * This structure is used to hold a virtual<->physical address
114 * association and is used mostly by bootstrap code
117 SLIST_ENTRY(pv_addr) pv_list;
127 vm_memattr_t pv_memattr;
128 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
129 vm_offset_t pv_kva; /* first kernel VA mapping */
131 TAILQ_HEAD(,pv_entry) pv_list;
139 * The number of L2 descriptor tables which can be tracked by an l2_dtable.
140 * A bucket size of 16 provides for 16MB of contiguous virtual address
141 * space per l2_dtable. Most processes will, therefore, require only two or
142 * three of these to map their whole working set.
144 #define L2_BUCKET_LOG2 4
145 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
147 * Given the above "L2-descriptors-per-l2_dtable" constant, the number
148 * of l2_dtable structures required to track all possible page descriptors
149 * mappable by an L1 translation table is given by the following constants:
151 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
152 #define L2_SIZE (1 << L2_LOG2)
157 struct l1_ttable *pm_l1;
158 struct l2_dtable *pm_l2[L2_SIZE];
159 cpuset_t pm_active; /* active on cpus */
160 struct pmap_statistics pm_stats; /* pmap statictics */
161 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
162 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
164 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
168 typedef struct pmap *pmap_t;
171 extern struct pmap kernel_pmap_store;
172 #define kernel_pmap (&kernel_pmap_store)
173 #define pmap_kernel() kernel_pmap
175 #define PMAP_ASSERT_LOCKED(pmap) \
176 mtx_assert(&(pmap)->pm_mtx, MA_OWNED)
177 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
178 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
179 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
180 NULL, MTX_DEF | MTX_DUPOK)
181 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx)
182 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
183 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
184 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
189 * For each vm_page_t, there is a list of all currently valid virtual
190 * mappings of that page. An entry is a pv_entry_t, the list is pv_list.
192 typedef struct pv_entry {
193 vm_offset_t pv_va; /* virtual address for mapping */
194 TAILQ_ENTRY(pv_entry) pv_list;
195 int pv_flags; /* flags (wired, etc...) */
196 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
197 pmap_t pv_pmap; /* pmap where mapping lies */
198 TAILQ_ENTRY(pv_entry) pv_plist;
203 * pv_entries are allocated in chunks per-process. This avoids the
204 * need to track per-pmap assignments.
211 TAILQ_ENTRY(pv_chunk) pc_list;
212 uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */
213 uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */
214 TAILQ_ENTRY(pv_chunk) pc_lru;
215 struct pv_entry pc_pventry[_NPCPV];
220 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **);
223 * virtual address to page table entry and
224 * to physical address. Likewise for alternate address space.
225 * Note: these work recursively, thus vtopte of a pte will give
226 * the corresponding pde that in turn maps it.
230 * The current top of kernel VM.
232 extern vm_offset_t pmap_curmaxkvaddr;
236 void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
237 /* Virtual address to page table entry */
238 static __inline pt_entry_t *
239 vtopte(vm_offset_t va)
244 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE)
249 extern vm_paddr_t phys_avail[];
250 extern vm_offset_t virtual_avail;
251 extern vm_offset_t virtual_end;
253 void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt);
254 int pmap_change_attr(vm_offset_t, vm_size_t, int);
255 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
256 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa);
257 void pmap_kenter_device(vm_offset_t va, vm_paddr_t pa);
258 void *pmap_kenter_temp(vm_paddr_t pa, int i);
259 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa);
260 vm_paddr_t pmap_kextract(vm_offset_t va);
261 void pmap_kremove(vm_offset_t);
262 void *pmap_mapdev(vm_offset_t, vm_size_t);
263 void pmap_unmapdev(vm_offset_t, vm_size_t);
264 vm_page_t pmap_use_pt(pmap_t, vm_offset_t);
265 void pmap_debug(int);
266 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
267 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
269 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
270 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
272 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
274 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int);
275 int pmap_dmap_iscurrent(pmap_t pmap);
278 * Definitions for MMU domains
280 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */
281 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */
284 * The new pmap ensures that page-tables are always mapping Write-Thru.
285 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
288 * Unfortunately, not all CPUs have a write-through cache mode. So we
289 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
290 * and if there is the chance for PTE syncs to be needed, we define
291 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
294 extern int pmap_needs_pte_sync;
297 * These macros define the various bit masks in the PTE.
299 * We use these macros since we use different bits on different processor
303 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
304 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\
305 L1_S_XSCALE_TEX(TEX_XSCALE_T))
307 #define L2_L_CACHE_MASK_generic (L2_B|L2_C)
308 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \
309 L2_XSCALE_L_TEX(TEX_XSCALE_T))
311 #define L2_S_PROT_U_generic (L2_AP(AP_U))
312 #define L2_S_PROT_W_generic (L2_AP(AP_W))
313 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
315 #define L2_S_PROT_U_xscale (L2_AP0(AP_U))
316 #define L2_S_PROT_W_xscale (L2_AP0(AP_W))
317 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
319 #define L2_S_CACHE_MASK_generic (L2_B|L2_C)
320 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \
321 L2_XSCALE_T_TEX(TEX_XSCALE_X))
323 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
324 #define L1_S_PROTO_xscale (L1_TYPE_S)
326 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
327 #define L1_C_PROTO_xscale (L1_TYPE_C)
329 #define L2_L_PROTO (L2_TYPE_L)
331 #define L2_S_PROTO_generic (L2_TYPE_S)
332 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS)
335 * User-visible names for the ones that vary with MMU class.
337 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
338 #define L2_AP(x) (L2_AP0(x))
340 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
344 /* More than one MMU class configured; use variables. */
345 #define L2_S_PROT_U pte_l2_s_prot_u
346 #define L2_S_PROT_W pte_l2_s_prot_w
347 #define L2_S_PROT_MASK pte_l2_s_prot_mask
349 #define L1_S_CACHE_MASK pte_l1_s_cache_mask
350 #define L2_L_CACHE_MASK pte_l2_l_cache_mask
351 #define L2_S_CACHE_MASK pte_l2_s_cache_mask
353 #define L1_S_PROTO pte_l1_s_proto
354 #define L1_C_PROTO pte_l1_c_proto
355 #define L2_S_PROTO pte_l2_s_proto
357 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
358 #define L2_S_PROT_U L2_S_PROT_U_generic
359 #define L2_S_PROT_W L2_S_PROT_W_generic
360 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic
362 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
363 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
364 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
366 #define L1_S_PROTO L1_S_PROTO_generic
367 #define L1_C_PROTO L1_C_PROTO_generic
368 #define L2_S_PROTO L2_S_PROTO_generic
370 #elif ARM_MMU_XSCALE == 1
371 #define L2_S_PROT_U L2_S_PROT_U_xscale
372 #define L2_S_PROT_W L2_S_PROT_W_xscale
373 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
375 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
376 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
377 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
379 #define L1_S_PROTO L1_S_PROTO_xscale
380 #define L1_C_PROTO L1_C_PROTO_xscale
381 #define L2_S_PROTO L2_S_PROTO_xscale
383 #elif (ARM_MMU_V6 + ARM_MMU_V7) != 0
385 * AP[2:1] access permissions model:
387 * AP[2](APX) - Write Disable
388 * AP[1] - User Enable
389 * AP[0] - Reference Flag
391 * AP[2] AP[1] Kernel User
398 #define L2_S_PROT_R (0) /* kernel read */
399 #define L2_S_PROT_U (L2_AP0(2)) /* user read */
400 #define L2_S_REF (L2_AP0(1)) /* reference flag */
402 #define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R|L2_APX)
403 #define L2_S_EXECUTABLE(pte) (!(pte & L2_XN))
404 #define L2_S_WRITABLE(pte) (!(pte & L2_APX))
405 #define L2_S_REFERENCED(pte) (!!(pte & L2_S_REF))
408 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C)
409 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C)
410 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C)
412 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED)
413 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED)
414 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED)
417 #define L1_S_PROTO (L1_TYPE_S)
418 #define L1_C_PROTO (L1_TYPE_C)
419 #define L2_S_PROTO (L2_TYPE_S)
422 * Promotion to a 1MB (SECTION) mapping requires that the corresponding
423 * 4KB (SMALL) page mappings have identical settings for the following fields:
425 #define L2_S_PROMOTE (L2_S_REF | L2_SHARED | L2_S_PROT_MASK | \
429 * In order to compare 1MB (SECTION) entry settings with the 4KB (SMALL)
430 * page mapping it is necessary to read and shift appropriate bits from
431 * L1 entry to positions of the corresponding bits in the L2 entry.
433 #define L1_S_DEMOTE(l1pd) ((((l1pd) & L1_S_PROTO) >> 0) | \
434 (((l1pd) & L1_SHARED) >> 6) | \
435 (((l1pd) & L1_S_REF) >> 6) | \
436 (((l1pd) & L1_S_PROT_MASK) >> 6) | \
437 (((l1pd) & L1_S_XN) >> 4))
440 #define ARM_L1S_STRONG_ORD (0)
441 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
442 #define ARM_L1S_DEVICE_SHARE (L1_S_B)
443 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1))
444 #define ARM_L1S_NRML_IWT_OWT (L1_S_C)
445 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B)
446 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B)
448 #define ARM_L2L_STRONG_ORD (0)
449 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
450 #define ARM_L2L_DEVICE_SHARE (L2_B)
451 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1))
452 #define ARM_L2L_NRML_IWT_OWT (L2_C)
453 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B)
454 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B)
456 #define ARM_L2S_STRONG_ORD (0)
457 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
458 #define ARM_L2S_DEVICE_SHARE (L2_B)
459 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1))
460 #define ARM_L2S_NRML_IWT_OWT (L2_C)
461 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B)
462 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B)
464 #define ARM_L1S_STRONG_ORD (0)
465 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
466 #define ARM_L1S_DEVICE_SHARE (L1_S_B)
467 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED)
468 #define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED)
469 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED)
470 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
472 #define ARM_L2L_STRONG_ORD (0)
473 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
474 #define ARM_L2L_DEVICE_SHARE (L2_B)
475 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED)
476 #define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED)
477 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
478 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
480 #define ARM_L2S_STRONG_ORD (0)
481 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
482 #define ARM_L2S_DEVICE_SHARE (L2_B)
483 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED)
484 #define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED)
485 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
486 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
488 #endif /* ARM_NMMUS > 1 */
490 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
491 #define PMAP_NEEDS_PTE_SYNC 1
492 #define PMAP_INCLUDE_PTE_SYNC
493 #elif defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A
494 #define PMAP_NEEDS_PTE_SYNC 1
495 #define PMAP_INCLUDE_PTE_SYNC
496 #elif (ARM_MMU_SA1 == 0)
497 #define PMAP_NEEDS_PTE_SYNC 0
501 * These macros return various bits based on kernel/user and protection.
502 * Note that the compiler will usually fold these at compile time.
504 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
506 #define L1_S_PROT_U (L1_S_AP(AP_U))
507 #define L1_S_PROT_W (L1_S_AP(AP_W))
508 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
509 #define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W)
511 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
512 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
514 #define L2_L_PROT_U (L2_AP(AP_U))
515 #define L2_L_PROT_W (L2_AP(AP_W))
516 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
518 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
519 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
521 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
522 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
524 #define L1_S_PROT_U (L1_S_AP(AP_U))
525 #define L1_S_PROT_W (L1_S_APX) /* Write disable */
526 #define L1_S_PROT_MASK (L1_S_PROT_W|L1_S_PROT_U)
527 #define L1_S_REF (L1_S_AP(AP_REF)) /* Reference flag */
528 #define L1_S_WRITABLE(pd) (!((pd) & L1_S_PROT_W))
529 #define L1_S_REFERENCED(pd) ((pd) & L1_S_REF)
531 #define L1_S_PROT(ku, pr) (((((ku) == PTE_KERNEL) ? 0 : L1_S_PROT_U) | \
532 (((pr) & VM_PROT_WRITE) ? 0 : L1_S_PROT_W) | \
533 (((pr) & VM_PROT_EXECUTE) ? 0 : L1_S_XN)))
535 #define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3))
536 #define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
537 (((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
539 #define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
540 (((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
545 * Macros to test if a mapping is mappable with an L1 Section mapping
546 * or an L2 Large Page mapping.
548 #define L1_S_MAPPABLE_P(va, pa, size) \
549 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
551 #define L2_L_MAPPABLE_P(va, pa, size) \
552 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
555 * Provide a fallback in case we were not able to determine it at
558 #ifndef PMAP_NEEDS_PTE_SYNC
559 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync
560 #define PMAP_INCLUDE_PTE_SYNC
564 #define _sync_l2(pte, size) cpu_l2cache_wb_range(vtophys(pte), size)
566 #define _sync_l2(pte, size) cpu_l2cache_wb_range(pte, size)
569 #define PTE_SYNC(pte) \
571 if (PMAP_NEEDS_PTE_SYNC) { \
572 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
573 cpu_drain_writebuf(); \
574 _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\
576 cpu_drain_writebuf(); \
577 } while (/*CONSTCOND*/0)
579 #define PTE_SYNC_RANGE(pte, cnt) \
581 if (PMAP_NEEDS_PTE_SYNC) { \
582 cpu_dcache_wb_range((vm_offset_t)(pte), \
583 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
584 cpu_drain_writebuf(); \
585 _sync_l2((vm_offset_t)(pte), \
586 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
588 cpu_drain_writebuf(); \
589 } while (/*CONSTCOND*/0)
591 extern pt_entry_t pte_l1_s_cache_mode;
592 extern pt_entry_t pte_l1_s_cache_mask;
594 extern pt_entry_t pte_l2_l_cache_mode;
595 extern pt_entry_t pte_l2_l_cache_mask;
597 extern pt_entry_t pte_l2_s_cache_mode;
598 extern pt_entry_t pte_l2_s_cache_mask;
600 extern pt_entry_t pte_l1_s_cache_mode_pt;
601 extern pt_entry_t pte_l2_l_cache_mode_pt;
602 extern pt_entry_t pte_l2_s_cache_mode_pt;
604 extern pt_entry_t pte_l2_s_prot_u;
605 extern pt_entry_t pte_l2_s_prot_w;
606 extern pt_entry_t pte_l2_s_prot_mask;
608 extern pt_entry_t pte_l1_s_proto;
609 extern pt_entry_t pte_l1_c_proto;
610 extern pt_entry_t pte_l2_s_proto;
612 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
613 extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
614 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
615 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
617 #if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
618 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
619 void pmap_zero_page_generic(vm_paddr_t, int, int);
621 void pmap_pte_init_generic(void);
622 #if defined(CPU_ARM8)
623 void pmap_pte_init_arm8(void);
625 #if defined(CPU_ARM9)
626 void pmap_pte_init_arm9(void);
627 #endif /* CPU_ARM9 */
628 #if defined(CPU_ARM10)
629 void pmap_pte_init_arm10(void);
630 #endif /* CPU_ARM10 */
631 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
632 void pmap_pte_init_mmu_v6(void);
633 #endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */
634 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
636 #if /* ARM_MMU_SA1 == */1
637 void pmap_pte_init_sa1(void);
638 #endif /* ARM_MMU_SA1 == 1 */
640 #if ARM_MMU_XSCALE == 1
641 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
642 void pmap_zero_page_xscale(vm_paddr_t, int, int);
644 void pmap_pte_init_xscale(void);
646 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t);
648 void pmap_use_minicache(vm_offset_t, vm_size_t);
649 #endif /* ARM_MMU_XSCALE == 1 */
650 #if defined(CPU_XSCALE_81342)
651 #define ARM_HAVE_SUPERSECTIONS
656 #define l1pte_valid(pde) ((pde) != 0)
657 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
658 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
659 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
661 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
662 #define l2pte_valid(pte) ((pte) != 0)
663 #define l2pte_pa(pte) ((pte) & L2_S_FRAME)
664 #define l2pte_minidata(pte) (((pte) & \
665 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
666 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
668 /* L1 and L2 page table macros */
669 #define pmap_pde_v(pde) l1pte_valid(*(pde))
670 #define pmap_pde_section(pde) l1pte_section_p(*(pde))
671 #define pmap_pde_page(pde) l1pte_page_p(*(pde))
672 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
674 #define pmap_pte_v(pte) l2pte_valid(*(pte))
675 #define pmap_pte_pa(pte) l2pte_pa(*(pte))
678 * Flags that indicate attributes of pages or mappings of pages.
680 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
681 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
682 * pv_entry's for each page. They live in the same "namespace" so
683 * that we can clear multiple attributes at a time.
685 * Note the "non-cacheable" flag generally means the page has
686 * multiple mappings in a given address space.
688 #define PVF_MOD 0x01 /* page is modified */
689 #define PVF_REF 0x02 /* page is referenced */
690 #define PVF_WIRED 0x04 /* mapping is wired */
691 #define PVF_WRITE 0x08 /* mapping is writable */
692 #define PVF_EXEC 0x10 /* mapping is executable */
693 #define PVF_NC 0x20 /* mapping is non-cacheable */
694 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */
695 #define PVF_UNMAN 0x80 /* mapping is unmanaged */
697 void vector_page_setprot(int);
700 * This structure is used by machine-dependent code to describe
701 * static mappings of devices, created at bootstrap time.
704 vm_offset_t pd_va; /* virtual address */
705 vm_paddr_t pd_pa; /* physical address */
706 vm_size_t pd_size; /* size of region */
707 vm_prot_t pd_prot; /* protection code */
708 int pd_cache; /* cache attributes */
711 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *);
713 #define SECTION_CACHE 0x1
714 #define SECTION_PT 0x2
715 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
716 #ifdef ARM_HAVE_SUPERSECTIONS
717 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags);
722 void pmap_postinit(void);
724 #ifdef ARM_USE_SMALL_ALLOC
725 void arm_add_smallalloc_pages(void *, void *, int, int);
726 vm_offset_t arm_ptovirt(vm_paddr_t);
727 void arm_init_smallalloc(void);
728 struct arm_small_page {
730 TAILQ_ENTRY(arm_small_page) pg_list;
735 extern vm_paddr_t dump_avail[];
740 #endif /* !_MACHINE_PMAP_H_ */