2 * Copyright (c) 1991 Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * the Systems Programming Group of the University of Utah Computer
7 * Science Department and William Jolitz of UUNET Technologies Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * Derived from hp300 version by Mike Hibler, this version by William
38 * Jolitz uses a recursive map [a pde points to the page directory] to
39 * map the page tables using the pagetables themselves. This is done to
40 * reduce the impact on kernel virtual memory for lots of sparse address
41 * space, and to reduce the cost of memory to each process.
43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
50 #ifndef _MACHINE_PMAP_H_
51 #define _MACHINE_PMAP_H_
53 #include <machine/pte.h>
54 #include <machine/cpuconf.h>
58 #if ARM_ARCH_6 || ARM_ARCH_7A
66 #define PTE_PAGETABLE 4
70 #define PTE_PAGETABLE 3
85 #include <sys/queue.h>
86 #include <sys/_cpuset.h>
87 #include <sys/_lock.h>
88 #include <sys/_mutex.h>
90 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */
91 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */
95 #define vtophys(va) pmap_kextract((vm_offset_t)(va))
99 #define pmap_page_get_memattr(m) ((m)->md.pv_memattr)
100 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
101 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
102 boolean_t pmap_page_is_mapped(vm_page_t);
104 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
106 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
113 * This structure is used to hold a virtual<->physical address
114 * association and is used mostly by bootstrap code
117 SLIST_ENTRY(pv_addr) pv_list;
127 vm_memattr_t pv_memattr;
128 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
129 vm_offset_t pv_kva; /* first kernel VA mapping */
131 TAILQ_HEAD(,pv_entry) pv_list;
139 * The number of L2 descriptor tables which can be tracked by an l2_dtable.
140 * A bucket size of 16 provides for 16MB of contiguous virtual address
141 * space per l2_dtable. Most processes will, therefore, require only two or
142 * three of these to map their whole working set.
144 #define L2_BUCKET_LOG2 4
145 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
147 * Given the above "L2-descriptors-per-l2_dtable" constant, the number
148 * of l2_dtable structures required to track all possible page descriptors
149 * mappable by an L1 translation table is given by the following constants:
151 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
152 #define L2_SIZE (1 << L2_LOG2)
157 struct l1_ttable *pm_l1;
158 struct l2_dtable *pm_l2[L2_SIZE];
159 cpuset_t pm_active; /* active on cpus */
160 struct pmap_statistics pm_stats; /* pmap statictics */
161 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
162 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
164 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
168 typedef struct pmap *pmap_t;
171 extern struct pmap kernel_pmap_store;
172 #define kernel_pmap (&kernel_pmap_store)
173 #define pmap_kernel() kernel_pmap
175 #define PMAP_ASSERT_LOCKED(pmap) \
176 mtx_assert(&(pmap)->pm_mtx, MA_OWNED)
177 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
178 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
179 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
180 NULL, MTX_DEF | MTX_DUPOK)
181 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx)
182 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
183 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
184 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
189 * For each vm_page_t, there is a list of all currently valid virtual
190 * mappings of that page. An entry is a pv_entry_t, the list is pv_list.
192 typedef struct pv_entry {
193 vm_offset_t pv_va; /* virtual address for mapping */
194 TAILQ_ENTRY(pv_entry) pv_list;
195 int pv_flags; /* flags (wired, etc...) */
196 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
197 pmap_t pv_pmap; /* pmap where mapping lies */
198 TAILQ_ENTRY(pv_entry) pv_plist;
203 * pv_entries are allocated in chunks per-process. This avoids the
204 * need to track per-pmap assignments.
211 TAILQ_ENTRY(pv_chunk) pc_list;
212 uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */
213 uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */
214 TAILQ_ENTRY(pv_chunk) pc_lru;
215 struct pv_entry pc_pventry[_NPCPV];
220 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **);
223 * virtual address to page table entry and
224 * to physical address. Likewise for alternate address space.
225 * Note: these work recursively, thus vtopte of a pte will give
226 * the corresponding pde that in turn maps it.
230 * The current top of kernel VM.
232 extern vm_offset_t pmap_curmaxkvaddr;
236 void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
237 /* Virtual address to page table entry */
238 static __inline pt_entry_t *
239 vtopte(vm_offset_t va)
244 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE)
249 extern vm_paddr_t phys_avail[];
250 extern vm_offset_t virtual_avail;
251 extern vm_offset_t virtual_end;
253 void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt);
254 int pmap_change_attr(vm_offset_t, vm_size_t, int);
255 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
256 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa);
257 void *pmap_kenter_temp(vm_paddr_t pa, int i);
258 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa);
259 vm_paddr_t pmap_kextract(vm_offset_t va);
260 void pmap_kremove(vm_offset_t);
261 void *pmap_mapdev(vm_offset_t, vm_size_t);
262 void pmap_unmapdev(vm_offset_t, vm_size_t);
263 vm_page_t pmap_use_pt(pmap_t, vm_offset_t);
264 void pmap_debug(int);
265 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
266 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
268 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
269 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
271 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
273 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int);
274 int pmap_dmap_iscurrent(pmap_t pmap);
277 * Definitions for MMU domains
279 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */
280 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */
283 * The new pmap ensures that page-tables are always mapping Write-Thru.
284 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
287 * Unfortunately, not all CPUs have a write-through cache mode. So we
288 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
289 * and if there is the chance for PTE syncs to be needed, we define
290 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
293 extern int pmap_needs_pte_sync;
296 * These macros define the various bit masks in the PTE.
298 * We use these macros since we use different bits on different processor
302 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
303 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\
304 L1_S_XSCALE_TEX(TEX_XSCALE_T))
306 #define L2_L_CACHE_MASK_generic (L2_B|L2_C)
307 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \
308 L2_XSCALE_L_TEX(TEX_XSCALE_T))
310 #define L2_S_PROT_U_generic (L2_AP(AP_U))
311 #define L2_S_PROT_W_generic (L2_AP(AP_W))
312 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
314 #define L2_S_PROT_U_xscale (L2_AP0(AP_U))
315 #define L2_S_PROT_W_xscale (L2_AP0(AP_W))
316 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
318 #define L2_S_CACHE_MASK_generic (L2_B|L2_C)
319 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \
320 L2_XSCALE_T_TEX(TEX_XSCALE_X))
322 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
323 #define L1_S_PROTO_xscale (L1_TYPE_S)
325 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
326 #define L1_C_PROTO_xscale (L1_TYPE_C)
328 #define L2_L_PROTO (L2_TYPE_L)
330 #define L2_S_PROTO_generic (L2_TYPE_S)
331 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS)
334 * User-visible names for the ones that vary with MMU class.
336 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
337 #define L2_AP(x) (L2_AP0(x))
339 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
343 /* More than one MMU class configured; use variables. */
344 #define L2_S_PROT_U pte_l2_s_prot_u
345 #define L2_S_PROT_W pte_l2_s_prot_w
346 #define L2_S_PROT_MASK pte_l2_s_prot_mask
348 #define L1_S_CACHE_MASK pte_l1_s_cache_mask
349 #define L2_L_CACHE_MASK pte_l2_l_cache_mask
350 #define L2_S_CACHE_MASK pte_l2_s_cache_mask
352 #define L1_S_PROTO pte_l1_s_proto
353 #define L1_C_PROTO pte_l1_c_proto
354 #define L2_S_PROTO pte_l2_s_proto
356 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
357 #define L2_S_PROT_U L2_S_PROT_U_generic
358 #define L2_S_PROT_W L2_S_PROT_W_generic
359 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic
361 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
362 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
363 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
365 #define L1_S_PROTO L1_S_PROTO_generic
366 #define L1_C_PROTO L1_C_PROTO_generic
367 #define L2_S_PROTO L2_S_PROTO_generic
369 #elif ARM_MMU_XSCALE == 1
370 #define L2_S_PROT_U L2_S_PROT_U_xscale
371 #define L2_S_PROT_W L2_S_PROT_W_xscale
372 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
374 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
375 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
376 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
378 #define L1_S_PROTO L1_S_PROTO_xscale
379 #define L1_C_PROTO L1_C_PROTO_xscale
380 #define L2_S_PROTO L2_S_PROTO_xscale
382 #elif (ARM_MMU_V6 + ARM_MMU_V7) != 0
384 * AP[2:1] access permissions model:
386 * AP[2](APX) - Write Disable
387 * AP[1] - User Enable
388 * AP[0] - Reference Flag
390 * AP[2] AP[1] Kernel User
397 #define L2_S_PROT_R (0) /* kernel read */
398 #define L2_S_PROT_U (L2_AP0(2)) /* user read */
399 #define L2_S_REF (L2_AP0(1)) /* reference flag */
401 #define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R|L2_APX)
402 #define L2_S_EXECUTABLE(pte) (!(pte & L2_XN))
403 #define L2_S_WRITABLE(pte) (!(pte & L2_APX))
404 #define L2_S_REFERENCED(pte) (!!(pte & L2_S_REF))
407 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C)
408 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C)
409 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C)
411 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED)
412 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED)
413 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED)
416 #define L1_S_PROTO (L1_TYPE_S)
417 #define L1_C_PROTO (L1_TYPE_C)
418 #define L2_S_PROTO (L2_TYPE_S)
421 * Promotion to a 1MB (SECTION) mapping requires that the corresponding
422 * 4KB (SMALL) page mappings have identical settings for the following fields:
424 #define L2_S_PROMOTE (L2_S_REF | L2_SHARED | L2_S_PROT_MASK | \
428 * In order to compare 1MB (SECTION) entry settings with the 4KB (SMALL)
429 * page mapping it is necessary to read and shift appropriate bits from
430 * L1 entry to positions of the corresponding bits in the L2 entry.
432 #define L1_S_DEMOTE(l1pd) ((((l1pd) & L1_S_PROTO) >> 0) | \
433 (((l1pd) & L1_SHARED) >> 6) | \
434 (((l1pd) & L1_S_REF) >> 6) | \
435 (((l1pd) & L1_S_PROT_MASK) >> 6) | \
436 (((l1pd) & L1_S_XN) >> 4))
439 #define ARM_L1S_STRONG_ORD (0)
440 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
441 #define ARM_L1S_DEVICE_SHARE (L1_S_B)
442 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1))
443 #define ARM_L1S_NRML_IWT_OWT (L1_S_C)
444 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B)
445 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B)
447 #define ARM_L2L_STRONG_ORD (0)
448 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
449 #define ARM_L2L_DEVICE_SHARE (L2_B)
450 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1))
451 #define ARM_L2L_NRML_IWT_OWT (L2_C)
452 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B)
453 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B)
455 #define ARM_L2S_STRONG_ORD (0)
456 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
457 #define ARM_L2S_DEVICE_SHARE (L2_B)
458 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1))
459 #define ARM_L2S_NRML_IWT_OWT (L2_C)
460 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B)
461 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B)
463 #define ARM_L1S_STRONG_ORD (0)
464 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
465 #define ARM_L1S_DEVICE_SHARE (L1_S_B)
466 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED)
467 #define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED)
468 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED)
469 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
471 #define ARM_L2L_STRONG_ORD (0)
472 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
473 #define ARM_L2L_DEVICE_SHARE (L2_B)
474 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED)
475 #define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED)
476 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
477 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
479 #define ARM_L2S_STRONG_ORD (0)
480 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
481 #define ARM_L2S_DEVICE_SHARE (L2_B)
482 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED)
483 #define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED)
484 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
485 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
487 #endif /* ARM_NMMUS > 1 */
489 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
490 #define PMAP_NEEDS_PTE_SYNC 1
491 #define PMAP_INCLUDE_PTE_SYNC
492 #elif defined(CPU_XSCALE_81342)
493 #define PMAP_NEEDS_PTE_SYNC 1
494 #define PMAP_INCLUDE_PTE_SYNC
495 #elif (ARM_MMU_SA1 == 0)
496 #define PMAP_NEEDS_PTE_SYNC 0
500 * These macros return various bits based on kernel/user and protection.
501 * Note that the compiler will usually fold these at compile time.
503 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
505 #define L1_S_PROT_U (L1_S_AP(AP_U))
506 #define L1_S_PROT_W (L1_S_AP(AP_W))
507 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
508 #define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W)
510 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
511 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
513 #define L2_L_PROT_U (L2_AP(AP_U))
514 #define L2_L_PROT_W (L2_AP(AP_W))
515 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
517 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
518 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
520 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
521 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
523 #define L1_S_PROT_U (L1_S_AP(AP_U))
524 #define L1_S_PROT_W (L1_S_APX) /* Write disable */
525 #define L1_S_PROT_MASK (L1_S_PROT_W|L1_S_PROT_U)
526 #define L1_S_REF (L1_S_AP(AP_REF)) /* Reference flag */
527 #define L1_S_WRITABLE(pd) (!((pd) & L1_S_PROT_W))
528 #define L1_S_REFERENCED(pd) ((pd) & L1_S_REF)
530 #define L1_S_PROT(ku, pr) (((((ku) == PTE_KERNEL) ? 0 : L1_S_PROT_U) | \
531 (((pr) & VM_PROT_WRITE) ? 0 : L1_S_PROT_W) | \
532 (((pr) & VM_PROT_EXECUTE) ? 0 : L1_S_XN)))
534 #define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3))
535 #define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
536 (((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
538 #define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
539 (((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
544 * Macros to test if a mapping is mappable with an L1 Section mapping
545 * or an L2 Large Page mapping.
547 #define L1_S_MAPPABLE_P(va, pa, size) \
548 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
550 #define L2_L_MAPPABLE_P(va, pa, size) \
551 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
554 * Provide a fallback in case we were not able to determine it at
557 #ifndef PMAP_NEEDS_PTE_SYNC
558 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync
559 #define PMAP_INCLUDE_PTE_SYNC
562 #define PTE_SYNC(pte) \
564 if (PMAP_NEEDS_PTE_SYNC) { \
565 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
566 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
568 cpu_drain_writebuf(); \
569 } while (/*CONSTCOND*/0)
571 #define PTE_SYNC_RANGE(pte, cnt) \
573 if (PMAP_NEEDS_PTE_SYNC) { \
574 cpu_dcache_wb_range((vm_offset_t)(pte), \
575 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
576 cpu_l2cache_wb_range((vm_offset_t)(pte), \
577 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
579 cpu_drain_writebuf(); \
580 } while (/*CONSTCOND*/0)
582 extern pt_entry_t pte_l1_s_cache_mode;
583 extern pt_entry_t pte_l1_s_cache_mask;
585 extern pt_entry_t pte_l2_l_cache_mode;
586 extern pt_entry_t pte_l2_l_cache_mask;
588 extern pt_entry_t pte_l2_s_cache_mode;
589 extern pt_entry_t pte_l2_s_cache_mask;
591 extern pt_entry_t pte_l1_s_cache_mode_pt;
592 extern pt_entry_t pte_l2_l_cache_mode_pt;
593 extern pt_entry_t pte_l2_s_cache_mode_pt;
595 extern pt_entry_t pte_l2_s_prot_u;
596 extern pt_entry_t pte_l2_s_prot_w;
597 extern pt_entry_t pte_l2_s_prot_mask;
599 extern pt_entry_t pte_l1_s_proto;
600 extern pt_entry_t pte_l1_c_proto;
601 extern pt_entry_t pte_l2_s_proto;
603 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
604 extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
605 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
606 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
608 #if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
609 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
610 void pmap_zero_page_generic(vm_paddr_t, int, int);
612 void pmap_pte_init_generic(void);
613 #if defined(CPU_ARM8)
614 void pmap_pte_init_arm8(void);
616 #if defined(CPU_ARM9)
617 void pmap_pte_init_arm9(void);
618 #endif /* CPU_ARM9 */
619 #if defined(CPU_ARM10)
620 void pmap_pte_init_arm10(void);
621 #endif /* CPU_ARM10 */
622 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
623 void pmap_pte_init_mmu_v6(void);
624 #endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */
625 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
627 #if /* ARM_MMU_SA1 == */1
628 void pmap_pte_init_sa1(void);
629 #endif /* ARM_MMU_SA1 == 1 */
631 #if ARM_MMU_XSCALE == 1
632 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
633 void pmap_zero_page_xscale(vm_paddr_t, int, int);
635 void pmap_pte_init_xscale(void);
637 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t);
639 void pmap_use_minicache(vm_offset_t, vm_size_t);
640 #endif /* ARM_MMU_XSCALE == 1 */
641 #if defined(CPU_XSCALE_81342)
642 #define ARM_HAVE_SUPERSECTIONS
647 #define l1pte_valid(pde) ((pde) != 0)
648 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
649 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
650 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
652 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
653 #define l2pte_valid(pte) ((pte) != 0)
654 #define l2pte_pa(pte) ((pte) & L2_S_FRAME)
655 #define l2pte_minidata(pte) (((pte) & \
656 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
657 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
659 /* L1 and L2 page table macros */
660 #define pmap_pde_v(pde) l1pte_valid(*(pde))
661 #define pmap_pde_section(pde) l1pte_section_p(*(pde))
662 #define pmap_pde_page(pde) l1pte_page_p(*(pde))
663 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
665 #define pmap_pte_v(pte) l2pte_valid(*(pte))
666 #define pmap_pte_pa(pte) l2pte_pa(*(pte))
669 * Flags that indicate attributes of pages or mappings of pages.
671 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
672 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
673 * pv_entry's for each page. They live in the same "namespace" so
674 * that we can clear multiple attributes at a time.
676 * Note the "non-cacheable" flag generally means the page has
677 * multiple mappings in a given address space.
679 #define PVF_MOD 0x01 /* page is modified */
680 #define PVF_REF 0x02 /* page is referenced */
681 #define PVF_WIRED 0x04 /* mapping is wired */
682 #define PVF_WRITE 0x08 /* mapping is writable */
683 #define PVF_EXEC 0x10 /* mapping is executable */
684 #define PVF_NC 0x20 /* mapping is non-cacheable */
685 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */
686 #define PVF_UNMAN 0x80 /* mapping is unmanaged */
688 void vector_page_setprot(int);
691 * This structure is used by machine-dependent code to describe
692 * static mappings of devices, created at bootstrap time.
695 vm_offset_t pd_va; /* virtual address */
696 vm_paddr_t pd_pa; /* physical address */
697 vm_size_t pd_size; /* size of region */
698 vm_prot_t pd_prot; /* protection code */
699 int pd_cache; /* cache attributes */
702 const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t);
703 const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t);
705 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *);
706 void pmap_devmap_register(const struct pmap_devmap *);
708 #define SECTION_CACHE 0x1
709 #define SECTION_PT 0x2
710 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
711 #ifdef ARM_HAVE_SUPERSECTIONS
712 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags);
717 void pmap_postinit(void);
719 #ifdef ARM_USE_SMALL_ALLOC
720 void arm_add_smallalloc_pages(void *, void *, int, int);
721 vm_offset_t arm_ptovirt(vm_paddr_t);
722 void arm_init_smallalloc(void);
723 struct arm_small_page {
725 TAILQ_ENTRY(arm_small_page) pg_list;
730 #define ARM_NOCACHE_KVA_SIZE 0x1000000
731 extern vm_offset_t arm_nocache_startaddr;
732 void *arm_remap_nocache(void *, vm_size_t);
733 void arm_unmap_nocache(void *, vm_size_t);
735 extern vm_paddr_t dump_avail[];
740 #endif /* !_MACHINE_PMAP_H_ */