2 * Copyright (c) 1991 Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * the Systems Programming Group of the University of Utah Computer
7 * Science Department and William Jolitz of UUNET Technologies Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * Derived from hp300 version by Mike Hibler, this version by William
38 * Jolitz uses a recursive map [a pde points to the page directory] to
39 * map the page tables using the pagetables themselves. This is done to
40 * reduce the impact on kernel virtual memory for lots of sparse address
41 * space, and to reduce the cost of memory to each process.
43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
50 #ifndef _MACHINE_PMAP_H_
51 #define _MACHINE_PMAP_H_
53 #include <machine/pte.h>
54 #include <machine/cpuconf.h>
60 #define PTE_PAGETABLE 2
64 #include <sys/queue.h>
65 #include <sys/_lock.h>
66 #include <sys/_mutex.h>
68 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */
69 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */
73 #define vtophys(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va))
74 #define pmap_kextract(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va))
78 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
84 * This structure is used to hold a virtual<->physical address
85 * association and is used mostly by bootstrap code
88 SLIST_ENTRY(pv_addr) pv_list;
97 TAILQ_HEAD(,pv_entry) pv_list;
100 #define VM_MDPAGE_INIT(pg) \
102 TAILQ_INIT(&pg->pv_list); \
103 mtx_init(&(pg)->md_page.pvh_mtx, "MDPAGE Mutex", NULL, MTX_DEV);\
104 (pg)->mdpage.pvh_attrs = 0; \
105 } while (/*CONSTCOND*/0)
112 * The number of L2 descriptor tables which can be tracked by an l2_dtable.
113 * A bucket size of 16 provides for 16MB of contiguous virtual address
114 * space per l2_dtable. Most processes will, therefore, require only two or
115 * three of these to map their whole working set.
117 #define L2_BUCKET_LOG2 4
118 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
120 * Given the above "L2-descriptors-per-l2_dtable" constant, the number
121 * of l2_dtable structures required to track all possible page descriptors
122 * mappable by an L1 translation table is given by the following constants:
124 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
125 #define L2_SIZE (1 << L2_LOG2)
130 struct l1_ttable *pm_l1;
131 struct l2_dtable *pm_l2[L2_SIZE];
132 pd_entry_t *pm_pdir; /* KVA of page directory */
133 int pm_active; /* active on cpus */
134 struct pmap_statistics pm_stats; /* pmap statictics */
135 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
138 typedef struct pmap *pmap_t;
141 extern pmap_t kernel_pmap;
142 #define pmap_kernel() kernel_pmap
144 #define PMAP_ASSERT_LOCKED(pmap) \
145 mtx_assert(&(pmap)->pm_mtx, MA_OWNED)
146 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
147 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
148 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
149 NULL, MTX_DEF | MTX_DUPOK)
150 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx)
151 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
152 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
153 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
158 * For each vm_page_t, there is a list of all currently valid virtual
159 * mappings of that page. An entry is a pv_entry_t, the list is pv_list.
161 typedef struct pv_entry {
162 pmap_t pv_pmap; /* pmap where mapping lies */
163 vm_offset_t pv_va; /* virtual address for mapping */
164 TAILQ_ENTRY(pv_entry) pv_list;
165 TAILQ_ENTRY(pv_entry) pv_plist;
166 int pv_flags; /* flags (wired, etc...) */
169 #define PV_ENTRY_NULL ((pv_entry_t) 0)
173 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **);
176 * virtual address to page table entry and
177 * to physical address. Likewise for alternate address space.
178 * Note: these work recursively, thus vtopte of a pte will give
179 * the corresponding pde that in turn maps it.
183 * The current top of kernel VM.
185 extern vm_offset_t pmap_curmaxkvaddr;
189 void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
190 /* Virtual address to page table entry */
191 static __inline pt_entry_t *
192 vtopte(vm_offset_t va)
197 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE)
202 extern vm_offset_t phys_avail[];
203 extern vm_offset_t virtual_avail;
204 extern vm_offset_t virtual_end;
206 void pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *);
207 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
208 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa);
209 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa);
210 void pmap_kremove(vm_offset_t);
211 void *pmap_mapdev(vm_offset_t, vm_size_t);
212 void pmap_unmapdev(vm_offset_t, vm_size_t);
213 vm_page_t pmap_use_pt(pmap_t, vm_offset_t);
214 void pmap_debug(int);
215 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
216 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
217 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
219 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
221 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int);
224 * Definitions for MMU domains
226 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */
227 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */
230 * The new pmap ensures that page-tables are always mapping Write-Thru.
231 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
234 * Unfortunately, not all CPUs have a write-through cache mode. So we
235 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
236 * and if there is the chance for PTE syncs to be needed, we define
237 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
240 extern int pmap_needs_pte_sync;
243 * These macros define the various bit masks in the PTE.
245 * We use these macros since we use different bits on different processor
248 #define L1_S_PROT_U (L1_S_AP(AP_U))
249 #define L1_S_PROT_W (L1_S_AP(AP_W))
250 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
252 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
253 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\
254 L1_S_XSCALE_TEX(TEX_XSCALE_T))
256 #define L2_L_PROT_U (L2_AP(AP_U))
257 #define L2_L_PROT_W (L2_AP(AP_W))
258 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
260 #define L2_L_CACHE_MASK_generic (L2_B|L2_C)
261 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \
262 L2_XSCALE_L_TEX(TEX_XSCALE_T))
264 #define L2_S_PROT_U_generic (L2_AP(AP_U))
265 #define L2_S_PROT_W_generic (L2_AP(AP_W))
266 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
268 #define L2_S_PROT_U_xscale (L2_AP0(AP_U))
269 #define L2_S_PROT_W_xscale (L2_AP0(AP_W))
270 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
272 #define L2_S_CACHE_MASK_generic (L2_B|L2_C)
273 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \
274 L2_XSCALE_T_TEX(TEX_XSCALE_X))
276 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
277 #define L1_S_PROTO_xscale (L1_TYPE_S)
279 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
280 #define L1_C_PROTO_xscale (L1_TYPE_C)
282 #define L2_L_PROTO (L2_TYPE_L)
284 #define L2_S_PROTO_generic (L2_TYPE_S)
285 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS)
288 * User-visible names for the ones that vary with MMU class.
292 /* More than one MMU class configured; use variables. */
293 #define L2_S_PROT_U pte_l2_s_prot_u
294 #define L2_S_PROT_W pte_l2_s_prot_w
295 #define L2_S_PROT_MASK pte_l2_s_prot_mask
297 #define L1_S_CACHE_MASK pte_l1_s_cache_mask
298 #define L2_L_CACHE_MASK pte_l2_l_cache_mask
299 #define L2_S_CACHE_MASK pte_l2_s_cache_mask
301 #define L1_S_PROTO pte_l1_s_proto
302 #define L1_C_PROTO pte_l1_c_proto
303 #define L2_S_PROTO pte_l2_s_proto
305 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
306 #define L2_S_PROT_U L2_S_PROT_U_generic
307 #define L2_S_PROT_W L2_S_PROT_W_generic
308 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic
310 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
311 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
312 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
314 #define L1_S_PROTO L1_S_PROTO_generic
315 #define L1_C_PROTO L1_C_PROTO_generic
316 #define L2_S_PROTO L2_S_PROTO_generic
318 #elif ARM_MMU_XSCALE == 1
319 #define L2_S_PROT_U L2_S_PROT_U_xscale
320 #define L2_S_PROT_W L2_S_PROT_W_xscale
321 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
323 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
324 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
325 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
327 #define L1_S_PROTO L1_S_PROTO_xscale
328 #define L1_C_PROTO L1_C_PROTO_xscale
329 #define L2_S_PROTO L2_S_PROTO_xscale
331 #endif /* ARM_NMMUS > 1 */
333 #ifdef SKYEYE_WORKAROUNDS
334 #define PMAP_NEEDS_PTE_SYNC 1
335 #define PMAP_INCLUDE_PTE_SYNC
337 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
338 #define PMAP_NEEDS_PTE_SYNC 1
339 #define PMAP_INCLUDE_PTE_SYNC
340 #elif defined(CPU_XSCALE_81342)
341 #define PMAP_NEEDS_PTE_SYNC 1
342 #define PMAP_INCLUDE_PTE_SYNC
343 #elif (ARM_MMU_SA1 == 0)
344 #define PMAP_NEEDS_PTE_SYNC 0
349 * These macros return various bits based on kernel/user and protection.
350 * Note that the compiler will usually fold these at compile time.
352 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
353 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
355 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
356 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
358 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
359 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
362 * Macros to test if a mapping is mappable with an L1 Section mapping
363 * or an L2 Large Page mapping.
365 #define L1_S_MAPPABLE_P(va, pa, size) \
366 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
368 #define L2_L_MAPPABLE_P(va, pa, size) \
369 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
372 * Provide a fallback in case we were not able to determine it at
375 #ifndef PMAP_NEEDS_PTE_SYNC
376 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync
377 #define PMAP_INCLUDE_PTE_SYNC
380 #define PTE_SYNC(pte) \
382 if (PMAP_NEEDS_PTE_SYNC) { \
383 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
384 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
386 } while (/*CONSTCOND*/0)
388 #define PTE_SYNC_RANGE(pte, cnt) \
390 if (PMAP_NEEDS_PTE_SYNC) { \
391 cpu_dcache_wb_range((vm_offset_t)(pte), \
392 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
393 cpu_l2cache_wb_range((vm_offset_t)(pte), \
394 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
396 } while (/*CONSTCOND*/0)
398 extern pt_entry_t pte_l1_s_cache_mode;
399 extern pt_entry_t pte_l1_s_cache_mask;
401 extern pt_entry_t pte_l2_l_cache_mode;
402 extern pt_entry_t pte_l2_l_cache_mask;
404 extern pt_entry_t pte_l2_s_cache_mode;
405 extern pt_entry_t pte_l2_s_cache_mask;
407 extern pt_entry_t pte_l1_s_cache_mode_pt;
408 extern pt_entry_t pte_l2_l_cache_mode_pt;
409 extern pt_entry_t pte_l2_s_cache_mode_pt;
411 extern pt_entry_t pte_l2_s_prot_u;
412 extern pt_entry_t pte_l2_s_prot_w;
413 extern pt_entry_t pte_l2_s_prot_mask;
415 extern pt_entry_t pte_l1_s_proto;
416 extern pt_entry_t pte_l1_c_proto;
417 extern pt_entry_t pte_l2_s_proto;
419 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
420 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
422 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
423 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
424 void pmap_zero_page_generic(vm_paddr_t, int, int);
426 void pmap_pte_init_generic(void);
427 #if defined(CPU_ARM8)
428 void pmap_pte_init_arm8(void);
430 #if defined(CPU_ARM9)
431 void pmap_pte_init_arm9(void);
432 #endif /* CPU_ARM9 */
433 #if defined(CPU_ARM10)
434 void pmap_pte_init_arm10(void);
435 #endif /* CPU_ARM10 */
436 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
438 #if /* ARM_MMU_SA1 == */1
439 void pmap_pte_init_sa1(void);
440 #endif /* ARM_MMU_SA1 == 1 */
442 #if ARM_MMU_XSCALE == 1
443 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
444 void pmap_zero_page_xscale(vm_paddr_t, int, int);
446 void pmap_pte_init_xscale(void);
448 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t);
450 void pmap_use_minicache(vm_offset_t, vm_size_t);
451 #endif /* ARM_MMU_XSCALE == 1 */
452 #if defined(CPU_XSCALE_81342)
453 #define ARM_HAVE_SUPERSECTIONS
458 #define l1pte_valid(pde) ((pde) != 0)
459 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
460 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
461 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
463 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
464 #define l2pte_valid(pte) ((pte) != 0)
465 #define l2pte_pa(pte) ((pte) & L2_S_FRAME)
466 #define l2pte_minidata(pte) (((pte) & \
467 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
468 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
470 /* L1 and L2 page table macros */
471 #define pmap_pde_v(pde) l1pte_valid(*(pde))
472 #define pmap_pde_section(pde) l1pte_section_p(*(pde))
473 #define pmap_pde_page(pde) l1pte_page_p(*(pde))
474 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
476 #define pmap_pte_v(pte) l2pte_valid(*(pte))
477 #define pmap_pte_pa(pte) l2pte_pa(*(pte))
480 * Flags that indicate attributes of pages or mappings of pages.
482 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
483 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
484 * pv_entry's for each page. They live in the same "namespace" so
485 * that we can clear multiple attributes at a time.
487 * Note the "non-cacheable" flag generally means the page has
488 * multiple mappings in a given address space.
490 #define PVF_MOD 0x01 /* page is modified */
491 #define PVF_REF 0x02 /* page is referenced */
492 #define PVF_WIRED 0x04 /* mapping is wired */
493 #define PVF_WRITE 0x08 /* mapping is writable */
494 #define PVF_EXEC 0x10 /* mapping is executable */
495 #define PVF_NC 0x20 /* mapping is non-cacheable */
496 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */
498 void vector_page_setprot(int);
500 void pmap_update(pmap_t);
503 * This structure is used by machine-dependent code to describe
504 * static mappings of devices, created at bootstrap time.
507 vm_offset_t pd_va; /* virtual address */
508 vm_paddr_t pd_pa; /* physical address */
509 vm_size_t pd_size; /* size of region */
510 vm_prot_t pd_prot; /* protection code */
511 int pd_cache; /* cache attributes */
514 const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t);
515 const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t);
517 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *);
518 void pmap_devmap_register(const struct pmap_devmap *);
520 #define SECTION_CACHE 0x1
521 #define SECTION_PT 0x2
522 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
523 #ifdef ARM_HAVE_SUPERSECTIONS
524 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags);
529 void pmap_postinit(void);
531 #ifdef ARM_USE_SMALL_ALLOC
532 void arm_add_smallalloc_pages(void *, void *, int, int);
533 vm_offset_t arm_ptovirt(vm_paddr_t);
534 void arm_init_smallalloc(void);
535 struct arm_small_page {
537 TAILQ_ENTRY(arm_small_page) pg_list;
542 #define ARM_NOCACHE_KVA_SIZE 0x1000000
543 extern vm_offset_t arm_nocache_startaddr;
544 void *arm_remap_nocache(void *, vm_size_t);
545 void arm_unmap_nocache(void *, vm_size_t);
547 extern vm_paddr_t dump_avail[];
552 #endif /* !_MACHINE_PMAP_H_ */