2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_PMAP_VAR_H_
31 #define _MACHINE_PMAP_VAR_H_
33 #include <machine/cpu-v6.h>
34 #include <machine/pte-v6.h>
36 * Various PMAP defines, exports, and inline functions
37 * definitions also usable in other MD code.
40 /* A number of pages in L1 page table. */
41 #define NPG_IN_PT1 (NB_IN_PT1 / PAGE_SIZE)
43 /* A number of L2 page tables in a page. */
44 #define NPT2_IN_PG (PAGE_SIZE / NB_IN_PT2)
46 /* A number of L2 page table entries in a page. */
47 #define NPTE2_IN_PG (NPT2_IN_PG * NPTE2_IN_PT2)
52 * A L2 page tables page contains NPT2_IN_PG L2 page tables. Masking of
53 * pte1_idx by PT2PG_MASK gives us an index to associated L2 page table
54 * in a page. The PT2PG_SHIFT definition depends on NPT2_IN_PG strictly.
55 * I.e., (1 << PT2PG_SHIFT) == NPT2_IN_PG must be fulfilled.
58 #define PT2PG_MASK ((1 << PT2PG_SHIFT) - 1)
61 * A PT2TAB holds all allocated L2 page table pages in a pmap.
62 * Right shifting of virtual address by PT2TAB_SHIFT gives us an index
63 * to L2 page table page in PT2TAB which holds the address mapping.
65 #define PT2TAB_ENTRIES (NPTE1_IN_PT1 / NPT2_IN_PG)
66 #define PT2TAB_SHIFT (PTE1_SHIFT + PT2PG_SHIFT)
69 * All allocated L2 page table pages in a pmap are mapped into PT2MAP space.
70 * An virtual address right shifting by PT2MAP_SHIFT gives us an index to PTE2
71 * which maps the address.
73 #define PT2MAP_SIZE (NPTE1_IN_PT1 * NB_IN_PT2)
74 #define PT2MAP_SHIFT PTE2_SHIFT
76 extern pt1_entry_t *kern_pt1;
77 extern pt2_entry_t *kern_pt2tab;
78 extern pt2_entry_t *PT2MAP;
81 * Virtual interface for L1 page table management.
85 pte1_index(vm_offset_t va)
88 return (va >> PTE1_SHIFT);
91 static __inline pt1_entry_t *
92 pte1_ptr(pt1_entry_t *pt1, vm_offset_t va)
95 return (pt1 + pte1_index(va));
98 static __inline vm_offset_t
99 pte1_trunc(vm_offset_t va)
102 return (va & PTE1_FRAME);
105 static __inline vm_offset_t
106 pte1_roundup(vm_offset_t va)
109 return ((va + PTE1_OFFSET) & PTE1_FRAME);
113 * Virtual interface for L1 page table entries management.
115 * XXX: Some of the following functions now with a synchronization barrier
116 * are called in a loop, so it could be useful to have two versions of them.
117 * One with the barrier and one without the barrier. In this case, pure
118 * barrier pte1_sync() should be implemented as well.
121 pte1_sync(pt1_entry_t *pte1p)
125 #ifndef PMAP_PTE_NOCACHE
126 if (!cpuinfo.coherent_walk)
127 dcache_wb_pou((vm_offset_t)pte1p, sizeof(*pte1p));
132 pte1_sync_range(pt1_entry_t *pte1p, vm_size_t size)
136 #ifndef PMAP_PTE_NOCACHE
137 if (!cpuinfo.coherent_walk)
138 dcache_wb_pou((vm_offset_t)pte1p, size);
143 pte1_store(pt1_entry_t *pte1p, pt1_entry_t pte1)
152 pte1_clear(pt1_entry_t *pte1p)
155 pte1_store(pte1p, 0);
159 pte1_clear_bit(pt1_entry_t *pte1p, uint32_t bit)
166 static __inline boolean_t
167 pte1_is_link(pt1_entry_t pte1)
170 return ((pte1 & L1_TYPE_MASK) == L1_TYPE_C);
174 pte1_is_section(pt1_entry_t pte1)
177 return ((pte1 & L1_TYPE_MASK) == L1_TYPE_S);
180 static __inline boolean_t
181 pte1_is_dirty(pt1_entry_t pte1)
184 return ((pte1 & (PTE1_NM | PTE1_RO)) == 0);
187 static __inline boolean_t
188 pte1_is_global(pt1_entry_t pte1)
191 return ((pte1 & PTE1_NG) == 0);
194 static __inline boolean_t
195 pte1_is_valid(pt1_entry_t pte1)
199 l1_type = pte1 & L1_TYPE_MASK;
200 return ((l1_type == L1_TYPE_C) || (l1_type == L1_TYPE_S));
203 static __inline boolean_t
204 pte1_is_wired(pt1_entry_t pte1)
207 return (pte1 & PTE1_W);
210 static __inline pt1_entry_t
211 pte1_load(pt1_entry_t *pte1p)
219 static __inline pt1_entry_t
220 pte1_load_clear(pt1_entry_t *pte1p)
231 pte1_set_bit(pt1_entry_t *pte1p, uint32_t bit)
238 static __inline vm_paddr_t
239 pte1_pa(pt1_entry_t pte1)
242 return ((vm_paddr_t)(pte1 & PTE1_FRAME));
245 static __inline vm_paddr_t
246 pte1_link_pa(pt1_entry_t pte1)
249 return ((vm_paddr_t)(pte1 & L1_C_ADDR_MASK));
253 * Virtual interface for L2 page table entries management.
255 * XXX: Some of the following functions now with a synchronization barrier
256 * are called in a loop, so it could be useful to have two versions of them.
257 * One with the barrier and one without the barrier.
261 pte2_sync(pt2_entry_t *pte2p)
265 #ifndef PMAP_PTE_NOCACHE
266 if (!cpuinfo.coherent_walk)
267 dcache_wb_pou((vm_offset_t)pte2p, sizeof(*pte2p));
272 pte2_sync_range(pt2_entry_t *pte2p, vm_size_t size)
276 #ifndef PMAP_PTE_NOCACHE
277 if (!cpuinfo.coherent_walk)
278 dcache_wb_pou((vm_offset_t)pte2p, size);
283 pte2_store(pt2_entry_t *pte2p, pt2_entry_t pte2)
292 pte2_clear(pt2_entry_t *pte2p)
295 pte2_store(pte2p, 0);
299 pte2_clear_bit(pt2_entry_t *pte2p, uint32_t bit)
306 static __inline boolean_t
307 pte2_is_dirty(pt2_entry_t pte2)
310 return ((pte2 & (PTE2_NM | PTE2_RO)) == 0);
313 static __inline boolean_t
314 pte2_is_global(pt2_entry_t pte2)
317 return ((pte2 & PTE2_NG) == 0);
320 static __inline boolean_t
321 pte2_is_valid(pt2_entry_t pte2)
324 return (pte2 & PTE2_V);
327 static __inline boolean_t
328 pte2_is_wired(pt2_entry_t pte2)
331 return (pte2 & PTE2_W);
334 static __inline pt2_entry_t
335 pte2_load(pt2_entry_t *pte2p)
343 static __inline pt2_entry_t
344 pte2_load_clear(pt2_entry_t *pte2p)
355 pte2_set_bit(pt2_entry_t *pte2p, uint32_t bit)
363 pte2_set_wired(pt2_entry_t *pte2p, boolean_t wired)
367 * Wired bit is transparent for page table walk,
368 * so pte2_sync() is not needed.
376 static __inline vm_paddr_t
377 pte2_pa(pt2_entry_t pte2)
380 return ((vm_paddr_t)(pte2 & PTE2_FRAME));
383 static __inline u_int
384 pte2_attr(pt2_entry_t pte2)
387 return ((u_int)(pte2 & PTE2_ATTR_MASK));
391 * Virtual interface for L2 page tables mapping management.
394 static __inline u_int
395 pt2tab_index(vm_offset_t va)
398 return (va >> PT2TAB_SHIFT);
401 static __inline pt2_entry_t *
402 pt2tab_entry(pt2_entry_t *pt2tab, vm_offset_t va)
405 return (pt2tab + pt2tab_index(va));
409 pt2tab_store(pt2_entry_t *pte2p, pt2_entry_t pte2)
412 pte2_store(pte2p,pte2);
415 static __inline pt2_entry_t
416 pt2tab_load(pt2_entry_t *pte2p)
419 return (pte2_load(pte2p));
422 static __inline pt2_entry_t
423 pt2tab_load_clear(pt2_entry_t *pte2p)
426 return (pte2_load_clear(pte2p));
429 static __inline u_int
430 pt2map_index(vm_offset_t va)
433 return (va >> PT2MAP_SHIFT);
436 static __inline pt2_entry_t *
437 pt2map_entry(vm_offset_t va)
440 return (PT2MAP + pt2map_index(va));
444 * Virtual interface for pmap structure & kernel shortcuts.
447 static __inline pt1_entry_t *
448 pmap_pte1(pmap_t pmap, vm_offset_t va)
451 return (pte1_ptr(pmap->pm_pt1, va));
454 static __inline pt1_entry_t *
455 kern_pte1(vm_offset_t va)
458 return (pte1_ptr(kern_pt1, va));
461 static __inline pt2_entry_t *
462 pmap_pt2tab_entry(pmap_t pmap, vm_offset_t va)
465 return (pt2tab_entry(pmap->pm_pt2tab, va));
468 static __inline pt2_entry_t *
469 kern_pt2tab_entry(vm_offset_t va)
472 return (pt2tab_entry(kern_pt2tab, va));
475 static __inline vm_page_t
476 pmap_pt2_page(pmap_t pmap, vm_offset_t va)
480 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
481 return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME));
484 static __inline vm_page_t
485 kern_pt2_page(vm_offset_t va)
489 pte2 = pte2_load(kern_pt2tab_entry(va));
490 return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME));
494 #endif /* !_MACHINE_PMAP_VAR_H_ */