2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_PMAP_VAR_H_
31 #define _MACHINE_PMAP_VAR_H_
33 #include <machine/cpu-v6.h>
35 * Various PMAP defines, exports, and inline functions
36 * definitions also usable in other MD code.
39 /* A number of pages in L1 page table. */
40 #define NPG_IN_PT1 (NB_IN_PT1 / PAGE_SIZE)
42 /* A number of L2 page tables in a page. */
43 #define NPT2_IN_PG (PAGE_SIZE / NB_IN_PT2)
45 /* A number of L2 page table entries in a page. */
46 #define NPTE2_IN_PG (NPT2_IN_PG * NPTE2_IN_PT2)
51 * A L2 page tables page contains NPT2_IN_PG L2 page tables. Masking of
52 * pte1_idx by PT2PG_MASK gives us an index to associated L2 page table
53 * in a page. The PT2PG_SHIFT definition depends on NPT2_IN_PG strictly.
54 * I.e., (1 << PT2PG_SHIFT) == NPT2_IN_PG must be fulfilled.
57 #define PT2PG_MASK ((1 << PT2PG_SHIFT) - 1)
60 * A PT2TAB holds all allocated L2 page table pages in a pmap.
61 * Right shifting of virtual address by PT2TAB_SHIFT gives us an index
62 * to L2 page table page in PT2TAB which holds the address mapping.
64 #define PT2TAB_ENTRIES (NPTE1_IN_PT1 / NPT2_IN_PG)
65 #define PT2TAB_SHIFT (PTE1_SHIFT + PT2PG_SHIFT)
68 * All allocated L2 page table pages in a pmap are mapped into PT2MAP space.
69 * An virtual address right shifting by PT2MAP_SHIFT gives us an index to PTE2
70 * which maps the address.
72 #define PT2MAP_SIZE (NPTE1_IN_PT1 * NB_IN_PT2)
73 #define PT2MAP_SHIFT PTE2_SHIFT
75 extern pt1_entry_t *kern_pt1;
76 extern pt2_entry_t *kern_pt2tab;
77 extern pt2_entry_t *PT2MAP;
80 * Virtual interface for L1 page table management.
84 pte1_index(vm_offset_t va)
87 return (va >> PTE1_SHIFT);
90 static __inline pt1_entry_t *
91 pte1_ptr(pt1_entry_t *pt1, vm_offset_t va)
94 return (pt1 + pte1_index(va));
97 static __inline vm_offset_t
98 pte1_trunc(vm_offset_t va)
101 return (va & PTE1_FRAME);
104 static __inline vm_offset_t
105 pte1_roundup(vm_offset_t va)
108 return ((va + PTE1_OFFSET) & PTE1_FRAME);
112 * Virtual interface for L1 page table entries management.
114 * XXX: Some of the following functions now with a synchronization barrier
115 * are called in a loop, so it could be useful to have two versions of them.
116 * One with the barrier and one without the barrier. In this case, pure
117 * barrier pte1_sync() should be implemented as well.
120 pte1_sync(pt1_entry_t *pte1p)
124 #ifndef PMAP_PTE_NOCACHE
125 if (!cpuinfo.coherent_walk)
126 dcache_wb_pou((vm_offset_t)pte1p, sizeof(*pte1p));
131 pte1_sync_range(pt1_entry_t *pte1p, vm_size_t size)
135 #ifndef PMAP_PTE_NOCACHE
136 if (!cpuinfo.coherent_walk)
137 dcache_wb_pou((vm_offset_t)pte1p, size);
142 pte1_store(pt1_entry_t *pte1p, pt1_entry_t pte1)
145 atomic_store_rel_int(pte1p, pte1);
150 pte1_clear(pt1_entry_t *pte1p)
153 pte1_store(pte1p, 0);
157 pte1_clear_bit(pt1_entry_t *pte1p, uint32_t bit)
160 atomic_clear_int(pte1p, bit);
164 static __inline boolean_t
165 pte1_cmpset(pt1_entry_t *pte1p, pt1_entry_t opte1, pt1_entry_t npte1)
169 ret = atomic_cmpset_int(pte1p, opte1, npte1);
170 if (ret) pte1_sync(pte1p);
175 static __inline boolean_t
176 pte1_is_link(pt1_entry_t pte1)
179 return ((pte1 & L1_TYPE_MASK) == L1_TYPE_C);
183 pte1_is_section(pt1_entry_t pte1)
186 return ((pte1 & L1_TYPE_MASK) == L1_TYPE_S);
189 static __inline boolean_t
190 pte1_is_dirty(pt1_entry_t pte1)
193 return ((pte1 & (PTE1_NM | PTE1_RO)) == 0);
196 static __inline boolean_t
197 pte1_is_global(pt1_entry_t pte1)
200 return ((pte1 & PTE1_NG) == 0);
203 static __inline boolean_t
204 pte1_is_valid(pt1_entry_t pte1)
208 l1_type = pte1 & L1_TYPE_MASK;
209 return ((l1_type == L1_TYPE_C) || (l1_type == L1_TYPE_S));
212 static __inline boolean_t
213 pte1_is_wired(pt1_entry_t pte1)
216 return (pte1 & PTE1_W);
219 static __inline pt1_entry_t
220 pte1_load(pt1_entry_t *pte1p)
228 static __inline pt1_entry_t
229 pte1_load_clear(pt1_entry_t *pte1p)
233 opte1 = atomic_readandclear_int(pte1p);
239 pte1_set_bit(pt1_entry_t *pte1p, uint32_t bit)
242 atomic_set_int(pte1p, bit);
246 static __inline vm_paddr_t
247 pte1_pa(pt1_entry_t pte1)
250 return ((vm_paddr_t)(pte1 & PTE1_FRAME));
253 static __inline vm_paddr_t
254 pte1_link_pa(pt1_entry_t pte1)
257 return ((vm_paddr_t)(pte1 & L1_C_ADDR_MASK));
261 * Virtual interface for L2 page table entries management.
263 * XXX: Some of the following functions now with a synchronization barrier
264 * are called in a loop, so it could be useful to have two versions of them.
265 * One with the barrier and one without the barrier.
269 pte2_sync(pt2_entry_t *pte2p)
273 #ifndef PMAP_PTE_NOCACHE
274 if (!cpuinfo.coherent_walk)
275 dcache_wb_pou((vm_offset_t)pte2p, sizeof(*pte2p));
280 pte2_sync_range(pt2_entry_t *pte2p, vm_size_t size)
284 #ifndef PMAP_PTE_NOCACHE
285 if (!cpuinfo.coherent_walk)
286 dcache_wb_pou((vm_offset_t)pte2p, size);
291 pte2_store(pt2_entry_t *pte2p, pt2_entry_t pte2)
294 atomic_store_rel_int(pte2p, pte2);
299 pte2_clear(pt2_entry_t *pte2p)
302 pte2_store(pte2p, 0);
306 pte2_clear_bit(pt2_entry_t *pte2p, uint32_t bit)
309 atomic_clear_int(pte2p, bit);
313 static __inline boolean_t
314 pte2_cmpset(pt2_entry_t *pte2p, pt2_entry_t opte2, pt2_entry_t npte2)
318 ret = atomic_cmpset_int(pte2p, opte2, npte2);
319 if (ret) pte2_sync(pte2p);
324 static __inline boolean_t
325 pte2_is_dirty(pt2_entry_t pte2)
328 return ((pte2 & (PTE2_NM | PTE2_RO)) == 0);
331 static __inline boolean_t
332 pte2_is_global(pt2_entry_t pte2)
335 return ((pte2 & PTE2_NG) == 0);
338 static __inline boolean_t
339 pte2_is_valid(pt2_entry_t pte2)
342 return (pte2 & PTE2_V);
345 static __inline boolean_t
346 pte2_is_wired(pt2_entry_t pte2)
349 return (pte2 & PTE2_W);
352 static __inline pt2_entry_t
353 pte2_load(pt2_entry_t *pte2p)
361 static __inline pt2_entry_t
362 pte2_load_clear(pt2_entry_t *pte2p)
366 opte2 = atomic_readandclear_int(pte2p);
372 pte2_set_bit(pt2_entry_t *pte2p, uint32_t bit)
375 atomic_set_int(pte2p, bit);
380 pte2_set_wired(pt2_entry_t *pte2p, boolean_t wired)
384 * Wired bit is transparent for page table walk,
385 * so pte2_sync() is not needed.
388 atomic_set_int(pte2p, PTE2_W);
390 atomic_clear_int(pte2p, PTE2_W);
393 static __inline vm_paddr_t
394 pte2_pa(pt2_entry_t pte2)
397 return ((vm_paddr_t)(pte2 & PTE2_FRAME));
400 static __inline u_int
401 pte2_attr(pt2_entry_t pte2)
404 return ((u_int)(pte2 & PTE2_ATTR_MASK));
408 * Virtual interface for L2 page tables mapping management.
411 static __inline u_int
412 pt2tab_index(vm_offset_t va)
415 return (va >> PT2TAB_SHIFT);
418 static __inline pt2_entry_t *
419 pt2tab_entry(pt2_entry_t *pt2tab, vm_offset_t va)
422 return (pt2tab + pt2tab_index(va));
426 pt2tab_store(pt2_entry_t *pte2p, pt2_entry_t pte2)
429 pte2_store(pte2p,pte2);
432 static __inline pt2_entry_t
433 pt2tab_load(pt2_entry_t *pte2p)
436 return (pte2_load(pte2p));
439 static __inline pt2_entry_t
440 pt2tab_load_clear(pt2_entry_t *pte2p)
443 return (pte2_load_clear(pte2p));
446 static __inline u_int
447 pt2map_index(vm_offset_t va)
450 return (va >> PT2MAP_SHIFT);
453 static __inline pt2_entry_t *
454 pt2map_entry(vm_offset_t va)
457 return (PT2MAP + pt2map_index(va));
461 * Virtual interface for pmap structure & kernel shortcuts.
464 static __inline pt1_entry_t *
465 pmap_pte1(pmap_t pmap, vm_offset_t va)
468 return (pte1_ptr(pmap->pm_pt1, va));
471 static __inline pt1_entry_t *
472 kern_pte1(vm_offset_t va)
475 return (pte1_ptr(kern_pt1, va));
478 static __inline pt2_entry_t *
479 pmap_pt2tab_entry(pmap_t pmap, vm_offset_t va)
482 return (pt2tab_entry(pmap->pm_pt2tab, va));
485 static __inline pt2_entry_t *
486 kern_pt2tab_entry(vm_offset_t va)
489 return (pt2tab_entry(kern_pt2tab, va));
492 static __inline vm_page_t
493 pmap_pt2_page(pmap_t pmap, vm_offset_t va)
497 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
498 return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME));
501 static __inline vm_page_t
502 kern_pt2_page(vm_offset_t va)
506 pte2 = pte2_load(kern_pt2tab_entry(va));
507 return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME));
511 #endif /* !_MACHINE_PMAP_VAR_H_ */