1 /* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */
4 * Copyright (c) 1994 Mark Brinicombe.
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8 * modification, are permitted provided that the following conditions
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14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the RiscBSD team.
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19 * endorse or promote products derived from this software without specific
20 * prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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37 #ifndef _MACHINE_PTE_H_
38 #define _MACHINE_PTE_H_
41 typedef uint32_t pd_entry_t; /* page directory entry */
42 typedef uint32_t pt_entry_t; /* page table entry */
45 #define PG_FRAME 0xfffff000
47 /* The PT_SIZE definition is misleading... A page table is only 0x400
48 * bytes long. But since VM mapping can only be done to 0x1000 a single
49 * 1KB blocks cannot be steered to a va by itself. Therefore the
50 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block
51 * was allocated for a PT then the other 3KB would also get mapped
52 * whenever the 1KB was mapped.
55 #define PT_RSIZE 0x0400 /* Real page table size */
56 #define PT_SIZE 0x1000
57 #define PD_SIZE 0x4000
59 /* Page table types and masks */
60 #define L1_PAGE 0x01 /* L1 page table mapping */
61 #define L1_SECTION 0x02 /* L1 section mapping */
62 #define L1_FPAGE 0x03 /* L1 fine page mapping */
63 #define L1_MASK 0x03 /* Mask for L1 entry type */
64 #define L2_LPAGE 0x01 /* L2 large page (64KB) */
65 #define L2_SPAGE 0x02 /* L2 small page (4KB) */
66 #define L2_MASK 0x03 /* Mask for L2 entry type */
67 #define L2_INVAL 0x00 /* L2 invalid type */
69 /* L1 and L2 address masks */
70 #define L1_ADDR_MASK 0xfffffc00
71 #define L2_ADDR_MASK 0xfffff000
74 * The ARM MMU architecture was introduced with ARM v3 (previous ARM
75 * architecture versions used an optional off-CPU memory controller
76 * to perform address translation).
78 * The ARM MMU consists of a TLB and translation table walking logic.
79 * There is typically one TLB per memory interface (or, put another
80 * way, one TLB per software-visible cache).
82 * The ARM MMU is capable of mapping memory in the following chunks:
84 * 1M Sections (L1 table)
86 * 64K Large Pages (L2 table)
88 * 4K Small Pages (L2 table)
90 * 1K Tiny Pages (L2 table)
92 * There are two types of L2 tables: Coarse Tables and Fine Tables.
93 * Coarse Tables can map Large and Small Pages. Fine Tables can
96 * Coarse Tables can define 4 Subpages within Large and Small pages.
97 * Subpages define different permissions for each Subpage within
100 * Coarse Tables are 1K in length. Fine tables are 4K in length.
102 * The Translation Table Base register holds the pointer to the
103 * L1 Table. The L1 Table is a 16K contiguous chunk of memory
104 * aligned to a 16K boundary. Each entry in the L1 Table maps
105 * 1M of virtual address space, either via a Section mapping or
108 * In addition, the Fast Context Switching Extension (FCSE) is available
109 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
110 * TLB/cache flushes on context switch by use of a smaller address space
111 * and a "process ID" that modifies the virtual address before being
112 * presented to the translation logic.
115 /* ARMv6 super-sections. */
116 #define L1_SUP_SIZE 0x01000000 /* 16M */
117 #define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
118 #define L1_SUP_FRAME (~L1_SUP_OFFSET)
119 #define L1_SUP_SHIFT 24
121 #define L1_S_SIZE 0x00100000 /* 1M */
122 #define L1_S_OFFSET (L1_S_SIZE - 1)
123 #define L1_S_FRAME (~L1_S_OFFSET)
124 #define L1_S_SHIFT 20
126 #define L2_L_SIZE 0x00010000 /* 64K */
127 #define L2_L_OFFSET (L2_L_SIZE - 1)
128 #define L2_L_FRAME (~L2_L_OFFSET)
129 #define L2_L_SHIFT 16
131 #define L2_S_SIZE 0x00001000 /* 4K */
132 #define L2_S_OFFSET (L2_S_SIZE - 1)
133 #define L2_S_FRAME (~L2_S_OFFSET)
134 #define L2_S_SHIFT 12
136 #define L2_T_SIZE 0x00000400 /* 1K */
137 #define L2_T_OFFSET (L2_T_SIZE - 1)
138 #define L2_T_FRAME (~L2_T_OFFSET)
139 #define L2_T_SHIFT 10
142 * The NetBSD VM implementation only works on whole pages (4K),
143 * whereas the ARM MMU's Coarse tables are sized in terms of 1K
144 * (16K L1 table, 1K L2 table).
146 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
149 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
150 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
152 #define L1_TABLE_SIZE 0x4000 /* 16K */
153 #define L2_TABLE_SIZE 0x1000 /* 4K */
155 * The new pmap deals with the 1KB coarse L2 tables by
156 * allocating them from a pool. Until every port has been converted,
157 * keep the old L2_TABLE_SIZE define lying around. Converted ports
158 * should use L2_TABLE_SIZE_REAL until then.
160 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */
166 #define L1_TYPE_INV 0x00 /* Invalid (fault) */
167 #define L1_TYPE_C 0x01 /* Coarse L2 */
168 #define L1_TYPE_S 0x02 /* Section */
169 #define L1_TYPE_F 0x03 /* Fine L2 */
170 #define L1_TYPE_MASK 0x03 /* mask of type bits */
172 /* L1 Section Descriptor */
173 #define L1_S_B 0x00000004 /* bufferable Section */
174 #define L1_S_C 0x00000008 /* cacheable Section */
175 #define L1_S_IMP 0x00000010 /* implementation defined */
176 #define L1_S_DOM(x) ((x) << 5) /* domain */
177 #define L1_S_DOM_MASK L1_S_DOM(0xf)
178 #define L1_S_AP(x) ((x) << 10) /* access permissions */
179 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
180 #define L1_S_TEX(x) (((x) & 0x7) << 12) /* Type Extension */
181 #define L1_S_TEX_MASK (0x7 << 12) /* Type Extension */
182 #define L1_S_APX (1 << 15)
183 #define L1_SHARED (1 << 16)
185 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
186 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */
188 #define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */
190 /* L1 Coarse Descriptor */
191 #define L1_C_IMP0 0x00000004 /* implementation defined */
192 #define L1_C_IMP1 0x00000008 /* implementation defined */
193 #define L1_C_IMP2 0x00000010 /* implementation defined */
194 #define L1_C_DOM(x) ((x) << 5) /* domain */
195 #define L1_C_DOM_MASK L1_C_DOM(0xf)
196 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
198 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */
200 /* L1 Fine Descriptor */
201 #define L1_F_IMP0 0x00000004 /* implementation defined */
202 #define L1_F_IMP1 0x00000008 /* implementation defined */
203 #define L1_F_IMP2 0x00000010 /* implementation defined */
204 #define L1_F_DOM(x) ((x) << 5) /* domain */
205 #define L1_F_DOM_MASK L1_F_DOM(0xf)
206 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
208 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */
214 #define L2_TYPE_INV 0x00 /* Invalid (fault) */
215 #define L2_TYPE_L 0x01 /* Large Page */
216 #define L2_TYPE_S 0x02 /* Small Page */
217 #define L2_TYPE_T 0x03 /* Tiny Page */
218 #define L2_TYPE_MASK 0x03 /* mask of type bits */
221 * This L2 Descriptor type is available on XScale processors
222 * when using a Coarse L1 Descriptor. The Extended Small
223 * Descriptor has the same format as the XScale Tiny Descriptor,
224 * but describes a 4K page, rather than a 1K page.
226 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */
228 #define L2_B 0x00000004 /* Bufferable page */
229 #define L2_C 0x00000008 /* Cacheable page */
230 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
231 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
232 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
233 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
235 #define L2_SHARED (1 << 10)
236 #define L2_APX (1 << 9)
237 #define L2_XN (1 << 0)
238 #define L2_L_TEX_MASK (0x7 << 12) /* Type Extension */
239 #define L2_L_TEX(x) (((x) & 0x7) << 12)
240 #define L2_S_TEX_MASK (0x7 << 6) /* Type Extension */
241 #define L2_S_TEX(x) (((x) & 0x7) << 6)
243 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */
244 #define L2_XSCALE_L_S(x) (1 << 15) /* Shared */
245 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */
248 * Access Permissions for L1 and L2 Descriptors.
250 #define AP_W 0x01 /* writable */
251 #define AP_U 0x02 /* user */
254 * Short-hand for common AP_* constants.
256 * Note: These values assume the S (System) bit is set and
257 * the R (ROM) bit is clear in CP15 register 1.
259 #define AP_KR 0x00 /* kernel read */
260 #define AP_KRW 0x01 /* kernel read/write */
261 #define AP_KRWUR 0x02 /* kernel read/write usr read */
262 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */
265 * Domain Types for the Domain Access Control Register.
267 #define DOMAIN_FAULT 0x00 /* no access */
268 #define DOMAIN_CLIENT 0x01 /* client */
269 #define DOMAIN_RESERVED 0x02 /* reserved */
270 #define DOMAIN_MANAGER 0x03 /* manager */
273 * Type Extension bits for XScale processors.
275 * Behavior of C and B when X == 0:
277 * C B Cacheable Bufferable Write Policy Line Allocate Policy
280 * 1 0 Y Y Write-through Read Allocate
281 * 1 1 Y Y Write-back Read Allocate
283 * Behavior of C and B when X == 1:
284 * C B Cacheable Bufferable Write Policy Line Allocate Policy
285 * 0 0 - - - - DO NOT USE
287 * 1 0 Mini-Data - - -
288 * 1 1 Y Y Write-back R/W Allocate
290 #define TEX_XSCALE_X 0x01 /* X modifies C and B */
291 #define TEX_XSCALE_E 0x02
292 #define TEX_XSCALE_T 0x04
298 * Cache attributes with L2 present, S = 0
299 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
300 * 0 0 0 0 0 N N - N N
301 * 0 0 0 0 1 N N - N Y
302 * 0 0 0 1 0 Y Y WT N Y
303 * 0 0 0 1 1 Y Y WB Y Y
304 * 0 0 1 0 0 N N - Y Y
305 * 0 0 1 0 1 N N - N N
306 * 0 0 1 1 0 Y Y - - N
307 * 0 0 1 1 1 Y Y WT Y Y
308 * 0 1 0 0 0 N N - N N
309 * 0 1 0 0 1 N/A N/A N/A N/A N/A
310 * 0 1 0 1 0 N/A N/A N/A N/A N/A
311 * 0 1 0 1 1 N/A N/A N/A N/A N/A
312 * 0 1 1 X X N/A N/A N/A N/A N/A
313 * 1 X 0 0 0 N N - N Y
314 * 1 X 0 0 1 Y N WB N Y
315 * 1 X 0 1 0 Y N WT N Y
316 * 1 X 0 1 1 Y N WB Y Y
317 * 1 X 1 0 0 N N - Y Y
318 * 1 X 1 0 1 Y Y WB Y Y
319 * 1 X 1 1 0 Y Y WT Y Y
320 * 1 X 1 1 1 Y Y WB Y Y
325 * Cache attributes with L2 present, S = 1
326 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
327 * 0 0 0 0 0 N N - N N
328 * 0 0 0 0 1 N N - N Y
329 * 0 0 0 1 0 Y Y - N Y
330 * 0 0 0 1 1 Y Y WT Y Y
331 * 0 0 1 0 0 N N - Y Y
332 * 0 0 1 0 1 N N - N N
333 * 0 0 1 1 0 Y Y - - N
334 * 0 0 1 1 1 Y Y WT Y Y
335 * 0 1 0 0 0 N N - N N
336 * 0 1 0 0 1 N/A N/A N/A N/A N/A
337 * 0 1 0 1 0 N/A N/A N/A N/A N/A
338 * 0 1 0 1 1 N/A N/A N/A N/A N/A
339 * 0 1 1 X X N/A N/A N/A N/A N/A
340 * 1 X 0 0 0 N N - N Y
341 * 1 X 0 0 1 Y N - N Y
342 * 1 X 0 1 0 Y N - N Y
343 * 1 X 0 1 1 Y N - Y Y
344 * 1 X 1 0 0 N N - Y Y
345 * 1 X 1 0 1 Y Y WT Y Y
346 * 1 X 1 1 0 Y Y WT Y Y
347 * 1 X 1 1 1 Y Y WT Y Y
349 #endif /* !_MACHINE_PTE_H_ */