2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <machine/intr.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/mmc/bridge.h>
49 #include <dev/mmc/mmcbrvar.h>
51 #include <arm/lpc/lpcreg.h>
52 #include <arm/lpc/lpcvar.h>
55 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
56 printf(fmt,##args); } while (0)
58 #define debugf(fmt, args...)
61 struct lpc_mmc_dmamap_arg {
62 bus_addr_t lm_dma_busaddr;
65 struct lpc_mmc_softc {
68 struct resource * lm_mem_res;
69 struct resource * lm_irq_res;
70 bus_space_tag_t lm_bst;
71 bus_space_handle_t lm_bsh;
73 struct mmc_host lm_host;
74 struct mmc_request * lm_req;
75 struct mmc_data * lm_data;
77 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
78 int lm_xfer_direction;
79 #define DIRECTION_READ 0
80 #define DIRECTION_WRITE 1
83 bus_dma_tag_t lm_dma_tag;
84 bus_dmamap_t lm_dma_map;
85 bus_addr_t lm_buffer_phys;
89 #define LPC_SD_MAX_BLOCKSIZE 1024
91 #define LPC_MMC_DMACH_READ 1
92 #define LPC_MMC_DMACH_WRITE 0
95 static int lpc_mmc_probe(device_t);
96 static int lpc_mmc_attach(device_t);
97 static int lpc_mmc_detach(device_t);
98 static void lpc_mmc_intr(void *);
100 static void lpc_mmc_cmd(struct lpc_mmc_softc *, struct mmc_command *);
101 static void lpc_mmc_setup_xfer(struct lpc_mmc_softc *, struct mmc_data *);
103 static int lpc_mmc_update_ios(device_t, device_t);
104 static int lpc_mmc_request(device_t, device_t, struct mmc_request *);
105 static int lpc_mmc_get_ro(device_t, device_t);
106 static int lpc_mmc_acquire_host(device_t, device_t);
107 static int lpc_mmc_release_host(device_t, device_t);
109 static void lpc_mmc_dma_rxfinish(void *);
110 static void lpc_mmc_dma_rxerror(void *);
111 static void lpc_mmc_dma_txfinish(void *);
112 static void lpc_mmc_dma_txerror(void *);
114 static void lpc_mmc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
116 #define lpc_mmc_lock(_sc) \
117 mtx_lock(&_sc->lm_mtx);
118 #define lpc_mmc_unlock(_sc) \
119 mtx_unlock(&_sc->lm_mtx);
120 #define lpc_mmc_read_4(_sc, _reg) \
121 bus_space_read_4(_sc->lm_bst, _sc->lm_bsh, _reg)
122 #define lpc_mmc_write_4(_sc, _reg, _value) \
123 bus_space_write_4(_sc->lm_bst, _sc->lm_bsh, _reg, _value)
125 static struct lpc_dmac_channel_config lpc_mmc_dma_rxconf = {
126 .ldc_fcntl = LPC_DMAC_FLOW_D_P2M,
127 .ldc_src_periph = LPC_DMAC_SD_ID,
128 .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
130 .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
131 .ldc_dst_periph = LPC_DMAC_SD_ID,
132 .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
134 .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
135 .ldc_success_handler = lpc_mmc_dma_rxfinish,
136 .ldc_error_handler = lpc_mmc_dma_rxerror,
139 static struct lpc_dmac_channel_config lpc_mmc_dma_txconf = {
140 .ldc_fcntl = LPC_DMAC_FLOW_P_M2P,
141 .ldc_src_periph = LPC_DMAC_SD_ID,
142 .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
144 .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
145 .ldc_dst_periph = LPC_DMAC_SD_ID,
146 .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
148 .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
149 .ldc_success_handler = lpc_mmc_dma_txfinish,
150 .ldc_error_handler = lpc_mmc_dma_txerror,
154 lpc_mmc_probe(device_t dev)
157 if (!ofw_bus_status_okay(dev))
160 if (!ofw_bus_is_compatible(dev, "lpc,mmc"))
163 device_set_desc(dev, "LPC32x0 MMC/SD controller");
164 return (BUS_PROBE_DEFAULT);
168 lpc_mmc_attach(device_t dev)
170 struct lpc_mmc_softc *sc = device_get_softc(dev);
171 struct lpc_mmc_dmamap_arg ctx;
178 mtx_init(&sc->lm_mtx, "lpcmmc", "mmc", MTX_DEF);
181 sc->lm_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
183 if (!sc->lm_mem_res) {
184 device_printf(dev, "cannot allocate memory window\n");
188 sc->lm_bst = rman_get_bustag(sc->lm_mem_res);
189 sc->lm_bsh = rman_get_bushandle(sc->lm_mem_res);
191 debugf("virtual register space: 0x%08lx\n", sc->lm_bsh);
194 sc->lm_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
196 if (!sc->lm_irq_res) {
197 device_printf(dev, "cannot allocate interrupt\n");
198 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
202 if (bus_setup_intr(dev, sc->lm_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
203 NULL, lpc_mmc_intr, sc, &sc->lm_intrhand))
205 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
206 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
207 device_printf(dev, "cannot setup interrupt handler\n");
211 sc->lm_host.f_min = 312500;
212 sc->lm_host.f_max = 2500000;
213 sc->lm_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 |
214 MMC_OCR_320_330 | MMC_OCR_330_340;
216 sc->lm_host.caps = MMC_CAP_4_BIT_DATA;
219 lpc_pwr_write(dev, LPC_CLKPWR_MS_CTRL,
220 LPC_CLKPWR_MS_CTRL_CLOCK_EN | LPC_CLKPWR_MS_CTRL_SD_CLOCK | 1);
221 lpc_mmc_write_4(sc, LPC_SD_POWER, LPC_SD_POWER_CTRL_ON);
223 device_set_ivars(dev, &sc->lm_host);
225 child = device_add_child(dev, "mmc", -1);
227 device_printf(dev, "attaching MMC bus failed!\n");
228 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
229 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
230 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
234 /* Alloc DMA memory */
235 err = bus_dma_tag_create(
236 bus_get_dma_tag(sc->lm_dev),
237 4, 0, /* alignment, boundary */
238 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
239 BUS_SPACE_MAXADDR, /* highaddr */
240 NULL, NULL, /* filter, filterarg */
241 LPC_SD_MAX_BLOCKSIZE, 1, /* maxsize, nsegments */
242 LPC_SD_MAX_BLOCKSIZE, 0, /* maxsegsize, flags */
243 NULL, NULL, /* lockfunc, lockarg */
246 err = bus_dmamem_alloc(sc->lm_dma_tag, (void **)&sc->lm_buffer,
249 device_printf(dev, "cannot allocate framebuffer\n");
253 err = bus_dmamap_load(sc->lm_dma_tag, sc->lm_dma_map, sc->lm_buffer,
254 LPC_SD_MAX_BLOCKSIZE, lpc_mmc_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
256 device_printf(dev, "cannot load DMA map\n");
260 sc->lm_buffer_phys = ctx.lm_dma_busaddr;
262 lpc_mmc_dma_rxconf.ldc_handler_arg = (void *)sc;
263 err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_READ, &lpc_mmc_dma_rxconf);
265 device_printf(dev, "cannot allocate RX DMA channel\n");
270 lpc_mmc_dma_txconf.ldc_handler_arg = (void *)sc;
271 err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_WRITE, &lpc_mmc_dma_txconf);
273 device_printf(dev, "cannot allocate TX DMA channel\n");
277 bus_generic_probe(dev);
278 bus_generic_attach(dev);
284 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
286 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
288 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
293 lpc_mmc_detach(device_t dev)
299 lpc_mmc_intr(void *arg)
301 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
302 struct mmc_command *cmd;
305 status = lpc_mmc_read_4(sc, LPC_SD_STATUS);
307 debugf("interrupt: 0x%08x\n", status);
309 if (status & LPC_SD_STATUS_CMDCRCFAIL) {
310 cmd = sc->lm_req->cmd;
311 cmd->error = sc->lm_flags & LPC_SD_FLAGS_IGNORECRC
312 ? MMC_ERR_NONE : MMC_ERR_BADCRC;
313 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
314 sc->lm_req->done(sc->lm_req);
316 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDCRCFAIL);
319 if (status & LPC_SD_STATUS_CMDACTIVE)
321 debugf("command active\n");
322 cmd = sc->lm_req->cmd;
323 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
324 sc->lm_req->done(sc->lm_req);
328 if (status & LPC_SD_STATUS_DATATIMEOUT) {
329 device_printf(sc->lm_dev, "data timeout\n");
330 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATATIMEOUT);
333 if (status & LPC_SD_STATUS_TXUNDERRUN) {
334 device_printf(sc->lm_dev, "TX underrun\n");
335 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_TXUNDERRUN);
338 if (status & LPC_SD_STATUS_CMDRESPEND) {
339 debugf("command response\n");
340 cmd = sc->lm_req->cmd;
342 if (cmd->flags & MMC_RSP_136) {
343 cmd->resp[3] = lpc_mmc_read_4(sc, LPC_SD_RESP3);
344 cmd->resp[2] = lpc_mmc_read_4(sc, LPC_SD_RESP2);
345 cmd->resp[1] = lpc_mmc_read_4(sc, LPC_SD_RESP1);
348 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
349 cmd->error = MMC_ERR_NONE;
351 if (cmd->data && (cmd->data->flags & MMC_DATA_WRITE))
352 lpc_mmc_setup_xfer(sc, sc->lm_req->cmd->data);
355 sc->lm_req->done(sc->lm_req);
359 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDRESPEND);
362 if (status & LPC_SD_STATUS_CMDSENT) {
363 debugf("command sent\n");
364 cmd = sc->lm_req->cmd;
365 cmd->error = MMC_ERR_NONE;
366 sc->lm_req->done(sc->lm_req);
368 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDSENT);
371 if (status & LPC_SD_STATUS_DATAEND) {
372 if (sc->lm_xfer_direction == DIRECTION_READ)
373 lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
375 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATAEND);
378 if (status & LPC_SD_STATUS_CMDTIMEOUT) {
379 device_printf(sc->lm_dev, "command response timeout\n");
380 cmd = sc->lm_req->cmd;
381 cmd->error = MMC_ERR_TIMEOUT;
382 sc->lm_req->done(sc->lm_req);
384 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDTIMEOUT);
388 if (status & LPC_SD_STATUS_STARTBITERR) {
389 device_printf(sc->lm_dev, "start bit error\n");
390 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_STARTBITERR);
393 if (status & LPC_SD_STATUS_DATACRCFAIL) {
394 device_printf(sc->lm_dev, "data CRC error\n");
395 debugf("data buffer: %p\n", sc->lm_buffer);
396 cmd = sc->lm_req->cmd;
397 cmd->error = MMC_ERR_BADCRC;
398 sc->lm_req->done(sc->lm_req);
401 if (sc->lm_xfer_direction == DIRECTION_READ)
402 lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
404 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATACRCFAIL);
407 if (status & LPC_SD_STATUS_DATABLOCKEND) {
408 debugf("data block end\n");
409 if (sc->lm_xfer_direction == DIRECTION_READ)
410 memcpy(sc->lm_data->data, sc->lm_buffer, sc->lm_data->len);
412 if (sc->lm_xfer_direction == DIRECTION_WRITE) {
413 lpc_dmac_disable_channel(sc->lm_dev, LPC_MMC_DMACH_WRITE);
414 lpc_mmc_write_4(sc, LPC_SD_DATACTRL, 0);
417 sc->lm_req->done(sc->lm_req);
419 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATABLOCKEND);
426 lpc_mmc_request(device_t bus, device_t child, struct mmc_request *req)
428 struct lpc_mmc_softc *sc = device_get_softc(bus);
430 debugf("request: %p\n", req);
438 if (req->cmd->data && req->cmd->data->flags & MMC_DATA_WRITE) {
439 memcpy(sc->lm_buffer, req->cmd->data->data, req->cmd->data->len);
440 lpc_mmc_cmd(sc, req->cmd);
446 lpc_mmc_setup_xfer(sc, req->cmd->data);
448 lpc_mmc_cmd(sc, req->cmd);
455 lpc_mmc_cmd(struct lpc_mmc_softc *sc, struct mmc_command *cmd)
459 debugf("cmd: %d arg: 0x%08x\n", cmd->opcode, cmd->arg);
461 if (lpc_mmc_read_4(sc, LPC_SD_COMMAND) & LPC_SD_COMMAND_ENABLE) {
462 lpc_mmc_write_4(sc, LPC_SD_COMMAND, 0);
466 sc->lm_flags &= ~LPC_SD_FLAGS_IGNORECRC;
468 if (cmd->flags & MMC_RSP_PRESENT)
469 cmdreg |= LPC_SD_COMMAND_RESPONSE;
471 if (MMC_RSP(cmd->flags) == MMC_RSP_R2)
472 cmdreg |= LPC_SD_COMMAND_LONGRSP;
474 if (MMC_RSP(cmd->flags) == MMC_RSP_R3)
475 sc->lm_flags |= LPC_SD_FLAGS_IGNORECRC;
477 cmdreg |= LPC_SD_COMMAND_ENABLE;
478 cmdreg |= (cmd->opcode & LPC_SD_COMMAND_CMDINDEXMASK);
480 lpc_mmc_write_4(sc, LPC_SD_MASK0, 0xffffffff);
481 lpc_mmc_write_4(sc, LPC_SD_MASK1, 0xffffffff);
482 lpc_mmc_write_4(sc, LPC_SD_ARGUMENT, cmd->arg);
483 lpc_mmc_write_4(sc, LPC_SD_COMMAND, cmdreg);
487 lpc_mmc_setup_xfer(struct lpc_mmc_softc *sc, struct mmc_data *data)
489 uint32_t datactrl = 0;
490 int data_words = data->len / 4;
493 sc->lm_xfer_done = 0;
495 debugf("data: %p, len: %d, %s\n", data,
496 data->len, (data->flags & MMC_DATA_READ) ? "read" : "write");
498 if (data->flags & MMC_DATA_READ) {
499 sc->lm_xfer_direction = DIRECTION_READ;
500 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ,
501 LPC_SD_PHYS_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
505 if (data->flags & MMC_DATA_WRITE) {
506 sc->lm_xfer_direction = DIRECTION_WRITE;
507 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE,
508 sc->lm_buffer_phys, LPC_SD_PHYS_BASE + LPC_SD_FIFO,
512 datactrl |= (sc->lm_xfer_direction
513 ? LPC_SD_DATACTRL_WRITE
514 : LPC_SD_DATACTRL_READ);
516 datactrl |= LPC_SD_DATACTRL_DMAENABLE | LPC_SD_DATACTRL_ENABLE;
517 datactrl |= (ffs(data->len) - 1) << 4;
519 debugf("datactrl: 0x%08x\n", datactrl);
521 lpc_mmc_write_4(sc, LPC_SD_DATATIMER, 0xFFFF0000);
522 lpc_mmc_write_4(sc, LPC_SD_DATALENGTH, data->len);
523 lpc_mmc_write_4(sc, LPC_SD_DATACTRL, datactrl);
527 lpc_mmc_read_ivar(device_t bus, device_t child, int which,
530 struct lpc_mmc_softc *sc = device_get_softc(bus);
535 case MMCBR_IVAR_BUS_MODE:
536 *(int *)result = sc->lm_host.ios.bus_mode;
538 case MMCBR_IVAR_BUS_WIDTH:
539 *(int *)result = sc->lm_host.ios.bus_width;
541 case MMCBR_IVAR_CHIP_SELECT:
542 *(int *)result = sc->lm_host.ios.chip_select;
544 case MMCBR_IVAR_CLOCK:
545 *(int *)result = sc->lm_host.ios.clock;
547 case MMCBR_IVAR_F_MIN:
548 *(int *)result = sc->lm_host.f_min;
550 case MMCBR_IVAR_F_MAX:
551 *(int *)result = sc->lm_host.f_max;
553 case MMCBR_IVAR_HOST_OCR:
554 *(int *)result = sc->lm_host.host_ocr;
556 case MMCBR_IVAR_MODE:
557 *(int *)result = sc->lm_host.mode;
560 *(int *)result = sc->lm_host.ocr;
562 case MMCBR_IVAR_POWER_MODE:
563 *(int *)result = sc->lm_host.ios.power_mode;
566 *(int *)result = sc->lm_host.ios.vdd;
568 case MMCBR_IVAR_CAPS:
569 *(int *)result = sc->lm_host.caps;
571 case MMCBR_IVAR_MAX_DATA:
580 lpc_mmc_write_ivar(device_t bus, device_t child, int which,
583 struct lpc_mmc_softc *sc = device_get_softc(bus);
588 case MMCBR_IVAR_BUS_MODE:
589 sc->lm_host.ios.bus_mode = value;
591 case MMCBR_IVAR_BUS_WIDTH:
592 sc->lm_host.ios.bus_width = value;
594 case MMCBR_IVAR_CHIP_SELECT:
595 sc->lm_host.ios.chip_select = value;
597 case MMCBR_IVAR_CLOCK:
598 sc->lm_host.ios.clock = value;
600 case MMCBR_IVAR_MODE:
601 sc->lm_host.mode = value;
604 sc->lm_host.ocr = value;
606 case MMCBR_IVAR_POWER_MODE:
607 sc->lm_host.ios.power_mode = value;
610 sc->lm_host.ios.vdd = value;
612 /* These are read-only */
613 case MMCBR_IVAR_CAPS:
614 case MMCBR_IVAR_HOST_OCR:
615 case MMCBR_IVAR_F_MIN:
616 case MMCBR_IVAR_F_MAX:
617 case MMCBR_IVAR_MAX_DATA:
624 lpc_mmc_update_ios(device_t bus, device_t child)
626 struct lpc_mmc_softc *sc = device_get_softc(bus);
627 struct mmc_ios *ios = &sc->lm_host.ios;
628 uint32_t clkdiv = 0, pwr = 0;
630 if (ios->bus_width == bus_width_4)
631 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
633 /* Calculate clock divider */
634 clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1;
636 /* Clock rate should not exceed rate requested in ios */
637 if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock)
640 debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv);
642 if (ios->bus_width == bus_width_4) {
643 debugf("using wide bus mode\n");
644 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
647 lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE);
649 switch (ios->power_mode) {
651 pwr |= LPC_SD_POWER_CTRL_OFF;
654 pwr |= LPC_SD_POWER_CTRL_UP;
657 pwr |= LPC_SD_POWER_CTRL_ON;
661 if (ios->bus_mode == opendrain)
662 pwr |= LPC_SD_POWER_OPENDRAIN;
664 lpc_mmc_write_4(sc, LPC_SD_POWER, pwr);
670 lpc_mmc_get_ro(device_t bus, device_t child)
677 lpc_mmc_acquire_host(device_t bus, device_t child)
679 struct lpc_mmc_softc *sc = device_get_softc(bus);
683 while (sc->lm_bus_busy)
684 error = mtx_sleep(sc, &sc->lm_mtx, PZERO, "mmcah", 0);
692 lpc_mmc_release_host(device_t bus, device_t child)
694 struct lpc_mmc_softc *sc = device_get_softc(bus);
703 static void lpc_mmc_dma_rxfinish(void *arg)
707 static void lpc_mmc_dma_rxerror(void *arg)
709 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
710 device_printf(sc->lm_dev, "DMA RX error\n");
713 static void lpc_mmc_dma_txfinish(void *arg)
717 static void lpc_mmc_dma_txerror(void *arg)
719 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
720 device_printf(sc->lm_dev, "DMA TX error\n");
724 lpc_mmc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
726 struct lpc_mmc_dmamap_arg *ctx;
731 ctx = (struct lpc_mmc_dmamap_arg *)arg;
732 ctx->lm_dma_busaddr = segs[0].ds_addr;
735 static device_method_t lpc_mmc_methods[] = {
736 /* Device interface */
737 DEVMETHOD(device_probe, lpc_mmc_probe),
738 DEVMETHOD(device_attach, lpc_mmc_attach),
739 DEVMETHOD(device_detach, lpc_mmc_detach),
742 DEVMETHOD(bus_read_ivar, lpc_mmc_read_ivar),
743 DEVMETHOD(bus_write_ivar, lpc_mmc_write_ivar),
745 /* MMC bridge interface */
746 DEVMETHOD(mmcbr_update_ios, lpc_mmc_update_ios),
747 DEVMETHOD(mmcbr_request, lpc_mmc_request),
748 DEVMETHOD(mmcbr_get_ro, lpc_mmc_get_ro),
749 DEVMETHOD(mmcbr_acquire_host, lpc_mmc_acquire_host),
750 DEVMETHOD(mmcbr_release_host, lpc_mmc_release_host),
755 static devclass_t lpc_mmc_devclass;
757 static driver_t lpc_mmc_driver = {
760 sizeof(struct lpc_mmc_softc),
763 DRIVER_MODULE(lpcmmc, simplebus, lpc_mmc_driver, lpc_mmc_devclass, NULL, NULL);
764 MMC_DECLARE_BRIDGE(lpcmmc);